Power semiconductors · AI data-center power · October 3, 2026
By Feifei Deng
The short answer: Renesas has launched the 650 V, 20 mΩ TP65H020G4PLSGBD-TR in an 8 × 8 mm dual-side-cooled PQFN and says samples are available now, while mass production is planned for mid-2027. Power-system engineers working on 800 V AI data-center architectures and buyers supporting those programs should treat this as a qualification window, not a production-availability signal: request traceable samples, confirm the exact -TR ordering code, and establish written production, packaging and regional availability milestones before committing a build.
What changed
On September 30, 2026, Renesas announced the TP65H020G4PLSGBD, a normally-off GaN switch built on its Gen IV Plus platform. The company positions the device for dense power conversion in 800 V high-voltage DC data-center systems. Its launch material names the intermediate bus converter, battery backup and capacitor-bank stages as target applications and describes conversion from an 800 V bus to 48 V, 12 V or 6 V rails.
The timing matters as much as the electrical headline. Renesas says the device is sampling today and plans mass production for mid-2027. The official part-details page still labels TP65H020G4PLSGBD-TR as “Preview.” It also says inventory may be available from authorized distributors, while pricing, availability and terms remain at each distributor’s discretion. That wording does not establish regional stock, a production lead time or a contractual delivery date.
For engineering teams, the practical opportunity is early access to a compact package and thermal concept that may suit space-constrained converters. For procurement teams, the practical risk is planning around an announced production date without written allocation, MOQ, reel quantity, price breaks or approved-channel availability. The right response is a controlled sample-and-validation program linked to explicit sourcing checkpoints.
What the exact TP65H020G4PLSGBD-TR part number establishes
The suffix is not optional purchasing shorthand. Renesas identifies TP65H020G4PLSGBD-TR as the tape-and-reel ordering code. The same official record lists a PQN88-IP dual-side-cooled package, 10 leads, an 8 × 8 mm body, surface-mount assembly, MSL 3 and an operating temperature range of −55 °C to +150 °C. It records a standard qualification level rather than an automotive qualification.
The published electrical snapshot includes a 650 V minimum drain-source rating, 20 mΩ typical and 25 mΩ maximum on-resistance, plus a 92 A current entry at 25 °C. Those numbers are not a design recipe. Current capability depends on the test condition, thermal path, switching frequency, gate drive, layout and protection strategy. Engineers should use the current official datasheet and models for design calculations, then verify performance on the intended stack-up and cooling assembly.
Renesas describes the normally-off implementation as a high-voltage depletion-mode GaN HEMT combined with a low-voltage silicon MOSFET. The company says it is compatible with standard silicon gate drivers and does not require a negative gate bias. That can reduce one adoption barrier, but it does not remove the need to review gate-loop inductance, dv/dt immunity, dead time, reverse conduction and abnormal operating conditions in the actual converter.
| Item to lock | Verified public position | Decision consequence |
|---|---|---|
| Exact orderable code | TP65H020G4PLSGBD-TR |
Keep the -TR suffix on the BOM, RFQ and sample record. |
| Package | PQN88-IP DSC, 8 × 8 mm, 10 leads | Review footprint, source-tab contact, cooling interfaces and assembly clearances. |
| Published state | Preview; sampling announced | Do not treat a sample as proof of production ATP. |
| Production plan | Mid-2027 | Build schedule checkpoints around written supplier updates. |
| Public commercial data | No fixed regional ATP, price or lead time | Request a dated quotation and authorized-channel confirmation. |
Engineering review priorities
The package is the central design change. Renesas reports that the 8 × 8 mm footprint is 57% smaller than its referenced 10 × 15 mm TOLT package and that dual-side cooling lowers top-side thermal impedance by 10%. These are manufacturer-reported comparisons, not guaranteed system-level improvements. The board, top-side interface, clamp pressure, heat spreader, airflow or liquid-cooling path and nearby copper all influence the result.
Start with the mechanical and thermal stack. Confirm the land pattern against the current package drawing, model solder-joint and board stress, define the top-side thermal interface and tolerance stack, and measure both steady-state and transient junction behavior. Include thermal cycling and power cycling appropriate to the intended duty profile. A compact package can save area while making alignment, flatness and interface control more sensitive.
Next, characterize the switching loop. Capture gate-source and drain-source waveforms with suitable high-bandwidth probes, measure overshoot and ringing across the expected input range, and verify short-circuit and overcurrent response. Review common-source inductance, return paths, driver placement and isolation. Renesas’ standard-driver compatibility is useful, but a previous silicon or GaN gate-drive design should not be copied without checking the new package and device behavior.
Finally, test the system outcome that matters. Renesas cites a 6 kW, 800 V-to-48 V LLC DC transformer reference design at 2.6 kW/in³ and reports full-load efficiency 0.21 percentage points above an equivalent TOLT-based board. Treat that as a reference-design result under Renesas’ conditions. Reproduce efficiency, temperature, EMI and fault performance in the target topology before changing the production BOM.
Sourcing plan before mass production
A useful RFQ separates samples from forecasted production demand. For samples, state the complete MPN, target quantity, delivery region, intended evaluation window and the need for manufacturer or authorized-distributor traceability. Ask for the sample lot, date code, reel or cut-tape format and any handling limits. Record which document revision supports the evaluation.
For production planning, request a dated statement covering the planned mass-production milestone, forecast acceptance, MOQ, standard pack, price breaks, quoted lead time, cancellation terms and allocation policy. The public product page does not supply those commitments. A distributor’s “inventory may be available” message is not equivalent to bookable ATP, and a sample shipment is not a production supply agreement.
Keep change control explicit. If another device is proposed for the footprint or electrical role, label it a candidate that requires validation unless the original manufacturer has formally established equivalence. Compare package drawing, pinout, gate behavior, dynamic characteristics, thermal interfaces, qualification level and reliability evidence. Do not merge base-part and -TR records in the BOM or quotation system.
If this device affects an upcoming build, send the exact MPN, forecast, target dates and application requirements for an updated component quotation. For a broader redesign, include the controlled BOM and PCBA constraints so sourcing and engineering review can run against the same revision; do not send customer-confidential design files unless they are required and covered by the proper channel.
Facts, judgment and recommendations
Verified facts: Renesas published the launch on September 30, 2026; the device is described as a 650 V, 20 mΩ GaN FET in an 8 × 8 mm dual-side-cooled PQFN; the exact -TR record specifies tape and reel; the status is Preview; sampling is underway; and mass production is planned for mid-2027.
Editorial judgment: The strongest immediate value is an early engineering and sourcing qualification window for 800 V data-center power programs. The public evidence does not support claims of broad stock, improving supply, falling prices, customer adoption, production yield or guaranteed availability.
Recommended actions: secure traceable samples, freeze the exact ordering code, review the complete thermal and gate-drive implementation, obtain a dated production quotation, and set a formal design-release gate tied to written supply evidence. These recommendations are a risk-control workflow, not a statement that the device is suitable for a specific design.
Frequently Asked Questions
Is TP65H020G4PLSGBD-TR in mass production?
No. Renesas says the device is sampling now and plans mass production for mid-2027. Its official part-details page currently shows Preview status.
What does the -TR suffix mean?
The official part-details page identifies TP65H020G4PLSGBD-TR as the tape-and-reel ordering code. Keep that suffix in the BOM and RFQ.
Does the announcement prove distributor stock or lead time?
No. Renesas says inventory may be available through authorized distributors, but pricing, availability and terms are set by each distributor. Request written, region-specific ATP and lead time.
Can an 8 × 8 mm GaN part replace a TOLT device directly?
Not on package size alone. Any alternative is a candidate that requires validation across footprint, pinout, gate behavior, thermal path, dynamic performance and qualification evidence.
What should be included in the first engineering review?
Review the current datasheet, footprint, top- and bottom-side cooling paths, interface pressure and tolerances, gate loop, switching waveforms, protection, EMI, thermal cycling and the production sourcing plan.
