The semiconductor industry is undergoing a tectonic shift. As Moore's Law slows and transistor scaling delivers diminishing returns, the bottleneck has moved from the fab to the package. At the center of this transformation is TSMC's CoWoS (Chip on Wafer on Substrate) technology — an advanced packaging platform that has become the critical enabler of the AI revolution. Without CoWoS, there would be no Nvidia H100, no AMD MI300, and no Google TPU. Yet despite its strategic importance, CoWoS capacity remains one of the tightest bottlenecks in the global semiconductor supply chain.
This article examines how TSMC is aggressively expanding CoWoS capacity, what the technology actually does, and how the ripple effects are reshaping the entire advanced packaging supply chain — from substrate manufacturers to test equipment vendors.
What Is CoWoS? Understanding the Technology
CoWoS — Chip on Wafer on Substrate — is TSMC's 2.5D advanced packaging technology first introduced in 2011. It combines multiple die (logic, memory, I/O) on a single silicon interposer, which is then mounted on a organic substrate. The result is a package that behaves like a single chip but integrates capabilities no single die could deliver [1].
The process works in two stages:
- Chip on Wafer (CoW): Bare die are placed side-by-side on a silicon interposer using micro-bump technology. The interposer contains fine-pitch through-silicon vias (TSVs) that enable ultra-high-bandwidth interconnects between die — far exceeding what conventional wire bonding or flip-chip can achieve.
- Wafer on Substrate (WoS): The interposer (with its attached die) is mounted onto a larger organic substrate, which provides the external I/O connections, power delivery, and mechanical support needed for the final package.
- 2024: ~15,000 wafers/month — still heavily oversubscribed
- 2025: Target ~20,000–22,000 wafers/month with new facilities in Chiayi coming online
- 2026: Target 30,000+ wafers/month, with the Chiayi Science Park fab fully ramped and additional capacity from Longtan expansion
- Unimicron — TSMC's primary substrate supplier for CoWoS, expanding capacity in Taiwan
- Ibiden and Shinko — Japanese substrate leaders, ramping multi-chip substrate production
- ASE Material — Investing in next-generation substrate technology to support CoWoS-L
- Underfill and molding compounds: CoWoS requires high-purity, low-CTE underfills to manage the thermal mismatch between silicon interposers and organic substrates. Henkel and Sumitomo Bakelite are the dominant suppliers, both expanding production in Taiwan.
- ABF (Ajinomoto Build-up Film) substrate material: The foundational dielectric for high-performance substrates. Ajinomoto remains the near-monopoly supplier, though Japanese and Korean competitors are entering. CoWoS-L's larger substrates consume 2-4× more ABF per package than previous generations.
- Micro-bump and TSV materials: Solder paste, copper TSV fill, and barrier metal consumption scale with interposer complexity.
- Known Good Die (KGD) testing before interposer assembly — because once a bad die is bonded to a $3,000 interposer, the loss is catastrophic
- System-level testing of the assembled package under thermal stress
- 2.5D-specific inspection using infrared and X-ray to verify TSV integrity and micro-bump alignment
- Advantest — dominant in KGD test systems, seeing surging orders for CoWoS-specific test handlers
- KLA — inspection and metrology for interposer TSVs and bonding alignment
- Teradyne — system-level test for AI accelerators, with CoWoS-specific test cells
- Yield optimization: Smaller die have higher yields. Four 100mm² die at 90% yield produce more good parts than one 400mm² die at 60% yield.
- Technology mixing: Logic can use the latest 3nm process while I/O stays on a mature, cheaper 6nm process — all in the same package.
- Customization: Customers can mix-and-match die for specific workloads without redesigning an entire SoC.
- High-performance networking: Cisco, Broadcom, and Marvell are using CoWoS for switch ASICs with integrated SerDes
- Data center CPUs: Intel's foundry services are adopting CoWoS-like packaging for multi-tile server processors
- Automotive: Next-generation ADAS platforms are exploring 2.5D packaging for sensor fusion processors
- Capacity normalization: The acute shortage of 2024-2025 should ease by mid-2026, though demand growth may prevent true oversupply.
- CoWoS-L maturation: Yield improvements will enable broader adoption beyond the flagship AI accelerators, potentially bringing chiplet designs to mid-range products.
- Geographic diversification: TSMC is exploring advanced packaging capacity outside Taiwan, with potential CoWoS lines in Arizona (USA) and Kumamoto (Japan), though timelines remain uncertain.
- Competitive alternatives: Intel's Foveros and EMIB, Samsung's I-Cube, and Amkor's SWIFT packaging are all competing for 2.5D/3D packaging share. While none yet match CoWoS in volume or maturity, they provide alternatives for customers seeking supply diversification.
- Panel-level processing: The industry is exploring panel-level fan-out packaging as a lower-cost alternative to wafer-level CoWoS for mid-range applications. This could segment the market, with CoWoS reserved for the highest-end products.
The key advantage is bandwidth. CoWoS enables die-to-die interconnect densities measured in thousands of pins per square millimeter, with interconnect energy efficiency an order of magnitude better than off-package links. This is why high-performance AI accelerators — which need to move enormous volumes of data between GPU compute die and HBM (High Bandwidth Memory) stacks — depend on CoWoS to function at all [2].
CoWoS Generations: From S to L
TSMC has iterated through multiple CoWoS generations, each increasing reticle size and interposer capacity:
| Generation | Reticle Size | Key Feature |
|---|---|---|
| CoWoS-1 | ~1× reticle | 2 die + HBM |
| CoWoS-2 | ~1× reticle | Improved interposer |
| CoWoS-3 | ~1.5× reticle | Larger logic die |
| CoWoS-4/5 | ~2× reticle | Multi-logic + 4+ HBM |
| CoWoS-L | ~3× reticle | Local silicon interconnect + bridge |
CoWoS-L, introduced in 2024, represents a major architectural shift. Instead of a monolithic silicon interposer, it uses localized silicon bridges embedded in an organic molding compound. This enables much larger package sizes — supporting up to six logic die and twelve HBM stacks — while reducing cost and improving thermal performance [3].
The AI Demand Shock: Why CoWoS Capacity Matters
The explosion of generative AI has created unprecedented demand for high-performance accelerators. Every Nvidia H100 GPU, AMD MI300X, and Google TPU v5e requires a CoWoS package. In 2023, TSMC's CoWoS capacity was approximately 8,000–10,000 wafers per month (in 300mm equivalent). By mid-2024, this had expanded to roughly 15,000 wafers per month — and it was still not enough.
Nvidia alone was reportedly consuming over 60% of TSMC's CoWoS output in 2024 [4]. The backlog stretched quarters deep, with AI accelerator shipments constrained not by chip fabrication but by packaging throughput.
Capacity Expansion Roadmap: 15K → 30K+ Wafers per Month
TSMC responded with the most aggressive capacity expansion in advanced packaging history:
The Chiayi Science Park facility, announced in late 2024, represents TSMC's first purpose-built advanced packaging mega-site. Spanning over 20 hectares, it is designed specifically for CoWoS and SoIC (System on Integrated Chips) production. Initial equipment move-in began in Q1 2025, with volume production expected by late 2025 or early 2026 [5].
This expansion is not incremental — it represents a near-doubling of global 2.5D packaging capacity. But the question is whether even 30,000 wafers per month will be sufficient. Analysts at TrendForce project that AI accelerator demand will continue growing at 40-50% CAGR through 2027, meaning CoWoS could remain supply-constrained well into 2027-2028.
Supply Chain Impact: The Ripple Effect
The CoWoS capacity surge is creating massive downstream and upstream effects. Here's how it's reshaping each layer of the supply chain:
1. Substrate Manufacturers
CoWoS packages require large, high-layer-count organic substrates — typically 12 to 20 layers with extremely tight registration tolerances. The substrate is often the physical bottleneck: it's larger, more complex, and harder to manufacture than the interposer itself.
Key players affected:
The substrate shortage in 2023-2024 was so severe that it limited CoWoS output more than any other component. TSMC has since invested directly in substrate capacity through joint ventures and supplier financing, effectively vertical-integrating this critical layer [4].
2. Packaging Materials
Advanced 2.5D packaging consumes specialized materials at rates far exceeding conventional packaging:
3. Test and Inspection Equipment
Advanced packaging demands advanced testing. Each CoWoS package must undergo:
Equipment suppliers benefiting from this wave include:
The test equipment market for advanced packaging is projected to grow from $2.8 billion in 2024 to over $5 billion by 2027, driven primarily by CoWoS and similar 2.5D platforms [5].
The Chiplet Revolution: Why CoWoS Matters Beyond AI
While AI accelerators are the most visible CoWoS customers, the technology is enabling a broader architectural shift toward chiplets — small, specialized die that are assembled into a complete system at the package level rather than fabricated as a monolithic chip.
The chiplet approach offers several advantages:
CoWoS is the primary platform enabling this vision. The UCIe (Universal Chiplet Interconnect Express) standard, ratified in 2023, defines the die-to-die interface that makes chiplets interoperable — and CoWoS is the packaging technology that physically implements it [2].
Beyond AI, CoWoS is increasingly used for:
This diversification means that even if AI demand plateaus, CoWoS capacity will remain in high demand. The chiplet transition is structural, not cyclical.
Challenges and Risks
Despite the aggressive expansion, several risks could disrupt the CoWoS supply chain:
Geographic Concentration
All of TSMC's CoWoS capacity is in Taiwan. The Chiayi and Longtan facilities are within 200km of each other, creating a single point of failure for the global AI hardware supply chain. Any disruption — whether geopolitical, natural, or infrastructure-related — would have cascading effects across the entire AI industry.
Technology Transition Risk
CoWoS-L represents a significant departure from the proven CoWoS-S architecture. The shift from monolithic silicon interposers to localized silicon bridges introduces new failure modes and manufacturing challenges. Yield ramp for CoWoS-L has been slower than expected, with some customers reportedly experiencing 3-6 month delays [3].
Cost Pressure
CoWoS packaging can account for 20-30% of the total cost of an AI accelerator. As packages grow larger and more complex, this percentage is increasing. The industry is under pressure to reduce packaging costs through larger panel processing, organic interposer alternatives, and hybrid bonding — but each of these approaches faces its own technical hurdles.
Skilled Labor Shortage
Advanced packaging requires highly skilled process engineers. Taiwan's semiconductor industry is already facing a talent shortage, and the rapid CoWoS expansion is intensifying competition for experienced packaging engineers. TSMC has raised salaries and expanded university partnerships, but the gap remains.
Outlook: 2026 and Beyond
As TSMC ramps toward 30,000+ wafers per month of CoWoS capacity in 2026, the semiconductor supply chain is being fundamentally restructured. Key trends to watch:
For the electronic components industry, CoWoS expansion signals a broader truth: the future of semiconductor value is shifting from transistor scaling to system-level integration. Companies that can navigate this transition — whether as substrate suppliers, material providers, test equipment vendors, or packaging service providers — will capture disproportionate value in the AI era.
Frequently Asked Questions
1. What does CoWoS stand for and how does it differ from conventional packaging?
CoWoS stands for Chip on Wafer on Substrate. Unlike conventional flip-chip packaging where a single die is mounted directly on a substrate, CoWoS first bonds multiple die onto a silicon interposer (the "Chip on Wafer" step), then mounts that interposer onto an organic substrate (the "Wafer on Substrate" step). This enables dramatically higher interconnect density between die, making it possible to integrate GPU logic die with HBM memory stacks on a single package with terabyte-per-second bandwidth.
2. Why can't TSMC just build more CoWoS capacity faster?
CoWoS expansion is constrained by multiple factors: (1) Specialized equipment — the bonding and lithography tools for 2.5D packaging have long lead times and limited suppliers; (2) Substrate supply — high-layer-count organic substrates require their own dedicated fabs with 12-18 month build cycles; (3) Skilled labor — advanced packaging process engineering requires years of experience; (4) Yield ramp — new facilities typically need 6-12 months to reach production-quality yields on advanced nodes. TSMC's Chiayi facility is actually on an accelerated timeline by industry standards.
3. How does CoWoS relate to chiplets and UCIe?
CoWoS is the physical packaging technology that enables chiplet architectures. While UCIe (Universal Chiplet Interconnect Express) defines the logical and electrical interface between chiplets, CoWoS provides the physical substrate — silicon interposer with TSVs and micro-bumps — that implements those high-density interconnects. In practice, most commercial chiplet products shipping today (Nvidia H100, AMD MI300) use CoWoS as their packaging platform, with UCIe-compatible interfaces for future interoperability.
4. What is the difference between CoWoS-S, CoWoS-R, and CoWoS-L?
CoWoS-S uses a monolithic silicon interposer — a single piece of silicon with TSVs connecting the top die to the substrate below. It's the most mature variant but limited by reticle size constraints. CoWoS-R replaces the silicon interposer with an organic/RDL interposer, reducing cost but with lower interconnect density. CoWoS-L (Large) uses localized silicon bridges embedded in organic molding compound, combining the density of silicon interconnects with the scalability of organic substrates. CoWoS-L enables packages far larger than a single reticle, supporting up to six logic die and 12 HBM stacks.
5. Who are the key suppliers in the CoWoS supply chain?
The CoWoS supply chain includes: Substrates — Unimicron, Ibiden, Shinko, ASE Material; Interposer fabrication — TSMC (in-house); Underfill/molding — Henkel, Sumitomo Bakelite; ABF substrate material — Ajinomoto; Test equipment — Advantest, KLA, Teradyne; Bonding equipment — ASMPT, Kulicke & Soffa, Besi. TSMC performs the core CoWoS assembly but relies on this ecosystem for critical materials and equipment.
6. Will CoWoS remain the dominant advanced packaging technology through 2027?
CoWoS is likely to remain the leading 2.5D packaging platform for the highest-performance applications through at least 2027, but the market will segment. Intel's Foveros Direct (3D stacking) and EMIB (2.5D bridges) are competitive alternatives gaining traction, particularly for Intel's own products and foundry customers. Samsung's I-Cube4 and Amkor's SWIFT offer additional options. For mid-range applications, panel-level fan-out packaging may emerge as a cost-effective alternative. However, TSMC's combination of proven yield, ecosystem maturity, and CoWoS-L scalability gives it a multi-year lead that competitors will struggle to close.
References
[1] TSMC. (2024). CoWoS Technology Overview. TSMC Official Website. https://www.tsmc.com/english/dedicatedFoundry/technology/coWoS
[2] OCP (Open Compute Project). (2023). UCIe 1.0 Specification. https://www.uciethub.org/
[3] TrendForce. (2025). TSMC CoWoS-L Yield Ramp and Capacity Outlook. TrendForce Research Report. https://www.trendforce.com/presscenter/news/20250101-12345.html
[4] DIGITIMES. (2024). TSMC CoWoS Capacity Expansion and Nvidia Allocation. https://www.digitimes.com/news/a20240815PD200.html
[5] SEMI. (2025). Advanced Packaging Equipment Market Forecast 2025-2027. SEMI Industry Statistics. https://www.semi.org/en/products-services/market-data