Power Integrity (PI): PDN Design and Decoupling Network Optimization

By informic1

Keywords: power integrity, PDN design, decoupling network, PCB power distribution

Introduction

Power integrity (PI) has emerged as one of the most critical disciplines in high-speed PCB design, standing alongside signal integrity and electromagnetic compatibility as a pillar of system reliability. While signal integrity ensures that data reaches its destination cleanly, power integrity ensures that every component receives a stable, low-noise power supply under all operating conditions. The two are intimately connected: power delivery network (PDN) noise directly translates into signal jitter, timing margin loss, and EMI failures.

The challenge of power integrity has grown with each generation of electronic devices. Modern processors and FPGAs can draw transient currents exceeding 100 A with slew rates over 1000 A/μs. At these levels, even nanohenries of parasitic inductance in the PDN produce voltage transients that can cause false switching, brown-out resets, or catastrophic timing failures. Meanwhile, supply voltages have dropped from 5V to below 1V, meaning the acceptable ripple budget is now measured in millivolts rather than hundreds of millivolts.

This article provides a comprehensive framework for PDN design and decoupling network optimization. We cover PDN impedance analysis, the target impedance method, decoupling capacitor selection and placement, plane capacitance strategies, voltage regulator module (VRM) modeling, and measurement techniques. Whether you are designing a simple microcontroller board or a complex multi-rail FPGA system, these principles will help you achieve a robust power delivery network.

Understanding PDN Impedance

The Power Delivery Network as a System

A PDN is not simply a network of copper planes and capacitors—it is a complex, distributed electrical system that includes the voltage regulator module (VRM), bulk capacitors, PCB power and ground planes, decoupling capacitors, package-level inductance, and on-die capacitance. Each of these elements contributes to the total impedance seen by the load at different frequencies.

The goal of PDN design is to ensure that the impedance seen from the load's perspective remains below a target value across the entire frequency band of interest. This is known as the target impedance method, and it is the foundation of modern power integrity analysis.

Impedance vs. Frequency Behavior

The PDN impedance varies dramatically with frequency due to the different response characteristics of its components:

Frequency Range	Dominant PDN Element	Typical Impedance	Primary Challenge
DC – 100 kHz	VRM	< 1 mΩ	DC voltage drop, load regulation
100 kHz – 1 MHz	Bulk capacitors	1–10 mΩ	ESL, ESR selection
1 MHz – 100 MHz	Decoupling capacitors	5–50 mΩ	Capacitor placement, mounting inductance
100 MHz – 1 GHz	Plane capacitance	10–100 mΩ	Plane geometry, stackup design
> 1 GHz	Package and on-die capacitance	1–10 mΩ	IC package design (beyond PCB control)

Impedance Peaks and Anti-Resonance

The most dangerous condition in a PDN is anti-resonance—a frequency at which the impedance peaks sharply due to the interaction between capacitive and inductive elements. These peaks occur when the inductive reactance of one PDN element resonates with the capacitive reactance of another. For example, the ESL of a bulk capacitor can resonate with the capacitance of a decoupling capacitor, creating a high-impedance peak at the transition frequency between their effective ranges.

Anti-resonance peaks are problematic because they concentrate PDN noise at specific frequencies. If a processor's current transient happens to excite a peak, the resulting voltage ripple can be many times larger than the flat-impedance value. Careful selection of capacitor values and ESR is essential to damp these resonances.

The Target Impedance Method

Defining Target Impedance

The target impedance (Z_target) is the maximum allowable PDN impedance at the load, calculated from the acceptable voltage ripple and the transient current:

Z_target = (ΔV_allowed × VDD) / ΔI_transient

where: - ΔV_allowed = fractional ripple allowance (e.g., ±3% of VDD) - VDD = nominal supply voltage - ΔI_transient = peak transient current swing

For a modern FPGA core rail at 0.9V with ±3% ripple and 40 A transient current:

Z_target = (0.03 × 0.9V) / 40A = 0.675 mΩ

This extremely low impedance must be maintained from DC to the highest frequency of the load transient—often several GHz.

Frequency Range of Interest

The relevant frequency band for PDN design extends from DC to the knee frequency of the load transient:

f_knee = 0.35 / T_r

where T_r is the rise time of the current transient. For a modern processor with 1 ns current rise time, f_knee ≈ 350 MHz. Above this frequency, the load's on-die decoupling handles the remaining noise, and the PCB PDN has minimal influence.

Target Impedance Calculation by Application

Application	VDD (V)	Ripple Budget	ΔI (A)	Z_target (mΩ)	Frequency Range
Microcontroller (8-bit)	3.3	±5%	0.1	1650	DC – 10 MHz
ARM Cortex-A (mobile)	1.2	±3%	5	7.2	DC – 100 MHz
FPGA (mid-range)	1.0	±3%	20	1.5	DC – 500 MHz
FPGA (high-end)	0.9	±3%	60	0.45	DC – 1 GHz
Server CPU	0.8	±2%	150	0.11	DC – 2 GHz
DDR5 VDDQ	1.1	±3%	15	2.2	DC – 1.6 GHz

Decoupling Capacitor Selection

Capacitor Types and Characteristics

Decoupling capacitors are the workhorses of PDN design. Each type has distinct characteristics that make it suitable for a specific frequency range:

Capacitor Type	Capacitance Range	ESR (mΩ)	ESL (nH)	Effective Range	Typical Application
Aluminum electrolytic	100–10000 μF	20–100	5–20	DC – 100 kHz	Bulk energy storage
Polymer (tantalum/Al)	10–1000 μF	5–30	1–5	10 kHz – 1 MHz	Mid-frequency bulk
Ceramic X5R/X7R	0.1–100 μF	2–10	0.3–1.0	100 kHz – 500 MHz	PCB decoupling
Ceramic X7R (0201)	0.001–0.1 μF	5–30	0.2–0.5	10 MHz – 1 GHz	High-frequency decoupling
Inter-digitated (IDC)	0.01–0.1 μF	5–15	0.05–0.15	100 MHz – 3 GHz	Very high frequency
Embedded (plane)	1–100 nF	< 1	< 0.01	100 MHz – 10 GHz	Plane capacitance

The Multi-Value Decoupling Strategy

Traditional decoupling strategies use multiple capacitor values to cover different frequency ranges. A typical arrangement for a high-speed processor might include:

2 × 470 μF polymer: Bulk energy storage (10 kHz – 500 kHz)
4 × 47 μF ceramic X5R: Mid-frequency decoupling (100 kHz – 10 MHz)
8 × 4.7 μF ceramic X5R: High-frequency decoupling (1 MHz – 100 MHz)
12 × 0.1 μF ceramic X7R: Very high-frequency decoupling (10 MHz – 500 MHz)
8 × 0.01 μF ceramic X7R (0201): Extreme high-frequency (100 MHz – 1 GHz)

ESR and Damping

While low ESR is generally desirable for minimizing DC voltage drop, it can actually worsen PDN performance by reducing damping of anti-resonance peaks. Capacitors with very low ESR (ceramic X5R/X7R) combined with low-ESL mounting can create high-Q resonances with the plane inductance. Adding a small amount of series resistance (or selecting capacitors with moderate ESR) can dampen these resonances.

The optimal ESR for damping a parallel resonance between a capacitor and plane inductance is:

ESR_optimal = √(L_plane / C_cap)

Typical values are 0.1–1.0 Ω, which is higher than most ceramic capacitors' intrinsic ESR. This is why controlled-ESR capacitors (sometimes called "damping capacitors") are sometimes added specifically to reduce Q.

Decoupling Capacitor Placement Strategies

Minimizing Loop Inductance

The effectiveness of a decoupling capacitor is limited not by its capacitance but by the loop inductance of the path connecting it to the load. This loop includes:

The capacitor's intrinsic ESL
The via connecting the capacitor pad to the power plane
The power and ground plane pair
The via connecting the plane to the IC power pin
The IC package inductance

The total loop inductance determines the frequency above which the capacitor ceases to be effective. For a typical 0402 ceramic capacitor with a 0.3 mm via length:

Capacitor ESL: ~0.5 nH
Via inductance: ~0.2 nH
Plane spreading inductance: ~0.1 nH
Total loop: ~0.8 nH

This gives a self-resonant frequency of:

f_SR = 1 / (2π × √(L × C))

For 0.1 μF with 0.8 nH loop: f_SR ≈ 17.8 MHz

Above this frequency, the capacitor behaves as an inductor and provides no decoupling benefit.

Placement Best Practices

Place the smallest-value capacitors closest to the IC power pins. This minimizes the loop inductance for the highest-frequency capacitors.
Use power and ground vias adjacent to capacitor pads. Avoid routing from capacitor pad to a via through a trace—the trace adds inductance.
Use multiple vias per pad. Two or three vias in parallel reduce the via inductance significantly compared to a single via.
Place capacitors on the same side as the IC when possible. This avoids the additional via inductance of routing to the opposite side.
Distribute bulk capacitors around the periphery of the IC. Bulk capacitors provide energy storage and don't need to be as close as high-frequency decoupling.
Use power-ground via pairs close together. The closer the power and ground vias, the smaller the loop area and the lower the inductance.

Mounting Inductance by Capacitor Package

Package	Typical Mounting Inductance (nH)	Effective Frequency Limit (0.1 μF)	Recommended Application
0805	1.0–1.5	~12 MHz	Low-frequency bulk decoupling
0603	0.7–1.0	~16 MHz	General-purpose decoupling
0402	0.4–0.7	~22 MHz	High-frequency decoupling
0201	0.3–0.5	~28 MHz	Very high-frequency decoupling
01005	0.2–0.3	~35 MHz	Ultra-high-frequency (limited availability)
Inter-digitated (LGA)	0.05–0.15	> 100 MHz	Multi-GHz decoupling

Plane Capacitance and Stackup Design

Embedded Plane Capacitance

When two solid copper planes (power and ground) are placed very close together—typically 2–10 μm of dielectric—they form a distributed capacitor that provides exceptionally low inductance decoupling. This plane capacitance is effective at frequencies above the range of discrete capacitors (100 MHz to several GHz) because it has virtually no loop inductance.

The plane capacitance per unit area is:

C_plane = ε0 × εr × A / d

where d is the dielectric thickness between planes. For FR-4 (εr = 4.3) with 10 μm dielectric:

C_plane = 8.854 × 10⁻¹² × 4.3 / 10 × 10⁻⁶ = 3.8 nF per square inch

Stackup Strategies for PI

Stackup Type	Inter-Plane Dielectric	Plane Capacitance (per in²)	Effective Frequency	Cost Impact
Standard (4 mil prepreg)	~100 μm	0.38 nF	100–500 MHz	None
Close plane (2 mil)	~50 μm	0.76 nF	100 MHz–1 GHz	Low
Buried capacitance (ZBC)	10–20 μm	1.9–3.8 nF	100 MHz–5 GHz	Medium
Ultra-thin (HDK)	2–5 μm	7.6–19 nF	100 MHz–10 GHz	High
Discrete capacitors only	N/A	N/A	DC–500 MHz	Lowest

Plane Resonance Management

Power-ground plane pairs act as a parallel-plate transmission line that can resonate at frequencies where the plane dimensions equal multiples of half-wavelengths. These cavity resonances create impedance peaks that can be excited by load transients.

For a rectangular plane pair of dimensions a × b:

f_mn = (c / 2π√εr) × √((mπ/a)² + (nπ/b)²)

where m and n are integer mode numbers. For a 100 mm × 80 mm FR-4 board, the first resonance (1,0 mode) occurs at approximately 750 MHz.

Mitigation strategies for plane resonances include:

Adding lossy dielectric material between planes
Distributing decoupling capacitors across the plane area (not just near the IC)
Using EDA tools to simulate plane impedance and identify resonant modes
Adding damping resistors in series with selected decoupling capacitors

VRM Modeling and Considerations

VRM Output Impedance

The voltage regulator module is the first element in the PDN chain. At low frequencies (DC to ~100 kHz), the VRM actively regulates the output voltage and presents a very low output impedance. Above the regulator's bandwidth, the VRM becomes inductive, and its impedance rises.

A simple VRM model for PDN simulation includes:

R0: DC output resistance (typically 0.5–5 mΩ)
L0: Output inductance (typically 1–10 nH, including package and board trace inductance)
R1, L1: Filter inductor ESR and inductance
C_bulk: Output bulk capacitance
R_ESR: Bulk capacitor ESR

VRM Loop Bandwidth

The VRM's control loop bandwidth determines the frequency above which the regulator cannot respond to load transients. Typical VRM bandwidths are:

Linear regulators: 10 kHz – 1 MHz
Switching regulators (buck): 20–100 kHz
Point-of-load (POL) modules: 50–500 kHz
Advanced digital POL: 100 kHz – 1 MHz

Above the loop bandwidth, the VRM cannot supply transient current, and the PDN must rely on bulk and decoupling capacitors. This is why adequate capacitance is critical—there is often a gap between the VRM's effective frequency range and the first capacitor's effective range.

Load-Line Regulation (Droop)

Some VRMs implement load-line regulation (also called adaptive voltage positioning), which intentionally drops the output voltage slightly as load current increases. This has two PI benefits:

It reduces the peak voltage during load release (when current drops suddenly, causing voltage overshoot)
It allows a higher target impedance (Z_target = ΔV/ΔI is the same, but the allowed ΔV is split between static droop and dynamic ripple)

Measurement and Verification Techniques

Frequency-Domain Measurement: VNA

A vector network analyzer (VNA) measures PDN impedance by injecting a small RF signal and measuring the reflected response. The measurement is typically performed using a 2-port shature technique:

Connect Port 1 and Port 2 of the VNA to two adjacent points on the PDN
Calibrate the VNA at the probe tips
Measure S11 and S21 parameters
Convert to impedance: Z = 25 × S21 / (1 - S11)

This method provides accurate impedance measurements from a few kHz to several GHz and is the standard technique for PDN characterization in the frequency domain.

Time-Domain Measurement: Oscilloscope

Time-domain measurements capture the actual voltage transients that occur during load steps. A high-bandwidth oscilloscope (> 1 GHz) with a low-impedance probe (or direct SMA connection) measures the supply voltage at the load pins during:

Power-up and power-down sequences
Maximum load step events (simulated or actual)
Normal operation with representative workload

The measured voltage deviation should remain within the ripple budget at all times. Persistent ringing at specific frequencies indicates anti-resonance peaks in the PDN.

Comparison of Measurement Techniques

Technique	Frequency Range	Measurement Time	Accuracy	Equipment Cost	Best For
2-port VNA (shunt)	100 kHz – 3 GHz	30–60 min per rail	±5%	High ($50k+)	Impedance profiling
Bode-100 (dedicated)	1 Hz – 50 MHz	15–30 min per rail	±10%	Medium ($10k)	Low-frequency PDN
Oscilloscope (load step)	DC – 1 GHz	5–15 min per rail	±20%	Medium ($10k+)	Time-domain validation
Picotest probes	DC – 3 GHz	5 min per point	±5%	Low ($1k)	Targeted impedance checks
PDN probe (PDN-A)	DC – 4 GHz	5 min per point	±3%	Low ($2k)	Fast impedance screening

PDN Design Workflow

A systematic approach to PDN design ensures that all frequency ranges are covered and that problems are identified early:

Define requirements: Determine target impedance for each power rail based on voltage, ripple budget, and transient current.
Select VRM: Choose a regulator with adequate bandwidth and output capability for the load.
Design stackup: Place power and ground planes on closely spaced layers for plane capacitance. Consider ultra-thin dielectric materials for high-performance designs.
Plan decoupling network: Select capacitor values and quantities to cover the frequency range between the VRM bandwidth and the load's on-die capacitance. Use simulation to verify impedance.
Optimize placement: Place capacitors to minimize loop inductance, with the smallest values closest to the IC.
Simulate: Run frequency-domain PDN analysis using an EDA tool (Sigrity, SIwave, HyperLynx PI). Check for anti-resonance peaks and verify target impedance is met.
Verify on hardware: Measure PDN impedance on prototypes using VNA and time-domain load-step testing.
Iterate: If measured impedance exceeds target, adjust capacitor values, quantities, or placement. Re-measure to confirm improvement.

FAQ

Q1: What is target impedance in PDN design?

What is target impedance in PDN design?

Target impedance is the maximum allowable AC impedance of the power delivery network as seen from the load, calculated as Z_target = (ΔV_allowed × VDD) / ΔI_transient. It represents the impedance level below which the PDN must stay to ensure that transient load current does not cause voltage ripple exceeding the specified tolerance. The target must be maintained across the entire frequency band from DC to the knee frequency of the load transient. For modern high-performance processors, target impedance can be below 1 mΩ—a challenging requirement that demands careful capacitor selection, plane design, and placement optimization.

Q2: How many decoupling capacitors do I need for my design?

How many decoupling capacitors do I need for my design?

There is no universal answer—the number depends on the target impedance, the load transient characteristics, and the effectiveness of each capacitor. The proper approach is to start with the target impedance, identify the frequency range that each capacitor type can cover, and then select quantities to meet the impedance target at each frequency. A typical high-speed FPGA core rail might use 2–4 bulk capacitors (100–470 μF), 4–8 mid-range ceramics (10–47 μF), 8–16 high-frequency ceramics (0.1–4.7 μF), and 8–16 very-high-frequency ceramics (0.01–0.1 μF). Simulation is essential to verify that the selected network meets the target impedance without anti-resonance peaks.

Q3: What causes anti-resonance peaks in a PDN?

What causes anti-resonance peaks in a PDN?

Anti-resonance peaks occur when the inductive reactance of one PDN element resonates with the capacitive reactance of another element at a specific frequency. The most common cause is the transition between different capacitor values: the larger capacitor becomes inductive (above its self-resonant frequency) while the smaller capacitor is still capacitive, creating a parallel LC resonance. The peak impedance at this resonance can far exceed the target impedance. Other causes include plane cavity resonances and interactions between the VRM output inductance and bulk capacitance. Mitigation strategies include using multiple capacitor values with overlapping frequency ranges, selecting capacitors with appropriate ESR for damping, and adding controlled-ESR damping capacitors.

Q4: How does plane capacitance differ from discrete capacitor decoupling?

How does plane capacitance differ from discrete capacitor decoupling?

Plane capacitance is the distributed capacitance between two closely spaced solid copper planes (power and ground) in the PCB stackup. Unlike discrete capacitors, plane capacitance has virtually zero loop inductance because the current flows directly between the two planes over the entire overlap area. This makes plane capacitance effective at frequencies well above the range of discrete capacitors—typically 100 MHz to several GHz. The tradeoff is that plane capacitance values are small (typically 0.5–4 nF per square inch) compared to discrete capacitors (0.1–470 μF). Plane capacitance supplements rather than replaces discrete decoupling; the two work together to cover different frequency ranges.

Q5: What is the role of ESR in decoupling capacitor selection?

What is the role of ESR in decoupling capacitor selection?

ESR (equivalent series resistance) plays a dual role in PDN design. On one hand, low ESR is desirable because it minimizes the DC voltage drop across the capacitor and reduces I²R power dissipation. On the other hand, some ESR is beneficial because it provides damping for anti-resonance peaks. Very low ESR ceramic capacitors combined with low-ESL mounting can create high-Q resonances that produce sharp impedance peaks. The optimal ESR for damping a resonance is ESR_optimal = √(L/C), typically 0.1–1.0 Ω. This is higher than most ceramic capacitors' intrinsic ESR (2–30 mΩ), which is why controlled-ESR capacitors are sometimes added specifically for damping. The best practice is to mix capacitor types with different ESR values to achieve both low impedance and adequate damping.

Q6: How do I measure PDN impedance on a real PCB?

How do I measure PDN impedance on a real PCB?

The most accurate method is the 2-port VNA shunt technique: connect two VNA ports to adjacent points on the PDN (using SMA connectors or probe clips), and measure S-parameters. The impedance is calculated as Z = 25 × S21 / (1 - S11). This covers 100 kHz to 3+ GHz with ±5% accuracy. For time-domain verification, use an oscilloscope to measure voltage transients during load steps—persistent ringing indicates anti-resonance peaks. For quick checks, a dedicated PDN probe (such as Picotest's PDN-A) can measure impedance at specific points in minutes. Always calibrate at the probe tips to remove cable and fixture effects, and measure at the IC power pins (not at the VRM output) to capture the full PDN.

References

Meta Description: Master power integrity and PDN design: target impedance method, decoupling capacitor selection and placement, plane capacitance, VRM modeling, anti-resonance damping, and measurement techniques for high-speed PCBs.