When a power MOSFET, IGBT, or SiC device switches tens or hundreds of watts, the silicon die stays alive only because heat finds a path out. That path is described by thermal resistance — a single number that tells you how many degrees Celsius each watt of losses will raise the junction above ambient. Get it wrong, and the device degrades, derates, or fails outright. Get it right, and your design runs cool for decades.
This guide walks through the full thermal-resistance framework: what the data-sheet numbers mean, how to calculate junction temperature, how to select a heat sink, and how to verify the result with simulation and measurement.
1. What Is Thermal Resistance?
Thermal resistance (Rth, measured in °C/W or K/W) is the temperature rise per unit of heat power flowing through a material or interface. It behaves exactly like electrical resistance: temperature difference is voltage, heat flow is current, and thermal resistance is — well, resistance.
1.1 The Three Key Numbers
Every power device data sheet specifies at least two thermal resistance values, and a complete system model adds a third:
| Symbol | Name | Definition | Typical Value (TO-220) |
|---|---|---|---|
| Rth(JA) | Junction-to-Ambient | Total thermal resistance from the silicon die to the surrounding air, with the package mounted on a standard PCB and no external heat sink [1] | 62.5 °C/W |
| Rth(JC) | Junction-to-Case | Thermal resistance from the die to the external surface of the package (the tab or exposed pad) [2] | 1.0–2.5 °C/W |
| Rth(CS) | Case-to-Sink | Thermal resistance across the interface between the package surface and the heat sink (determined by thermal grease, pad, or phase-change material) [3] | 0.3–1.5 °C/W |
Rth(JA) is what you use when the device runs without a heat sink — bare package on a PCB. Rth(JC) + Rth(CS) + Rth(SA) is what you use with a heat sink, where Rth(SA) is the heat-sink-to-ambient resistance specified by the heat sink manufacturer.
Key point: Rth(JA) on the data sheet is measured on a specific board (usually JEDEC 51-7, 2s2p or 1s0p). Your actual board will differ. Always treat data-sheet Rth(JA) as a starting estimate, not a guaranteed value.
1.2 Junction Temperature Formula
The fundamental equation for junction temperature is:
Without heat sink:
Tj = Ta + P × Rth(JA)
With heat sink:
Tj = Ta + P × [Rth(JC) + Rth(CS) + Rth(SA)]
Where:
- Tj = junction temperature (°C)
- Ta = ambient temperature (°C)
- P = power dissipation (W)
- Rth(JC) = junction-to-case thermal resistance (°C/W)
- Rth(CS) = case-to-sink thermal resistance (°C/W)
- Rth(SA) = sink-to-ambient thermal resistance (°C/W)
Most silicon power devices have a maximum Tj of 150 °C (MOSFETs) or 175 °C (some IGBTs and SiC devices). Good design practice keeps Tj below 110–125 °C to ensure long-term reliability [4].
2. Thermal Resistance Calculation Step by Step
Step 1 — Determine Power Dissipation
For a switching power device, total losses are the sum of conduction and switching losses:
P_total = P_conduction + P_switching
For a MOSFET in a switching converter:
- P_conduction = I_rms² × R_DS(on) (use the R_DS(on) at the actual junction temperature — it roughly doubles from 25 °C to 125 °C)
- P_switching = ½ × V_DS × I_D × (t_rise + t_fall) × f_sw
If the device is a linear regulator or a resistive load element, P = V_drop × I_load is sufficient.
Step 2 — Choose Your Cooling Strategy
This determines which thermal resistance chain you use:
| Scenario | Use Rth(JA) | Use Rth(JC) + Rth(CS) + Rth(SA) |
|---|---|---|
| Bare device on PCB, no heat sink | ✅ | — |
| Device with bolted-on heat sink | — | ✅ |
| Device on thick copper pour, no sink | ✅ (but use PCB-specific Rth) | — |
| Device with factory thermal pad on chassis | — | ✅ |
Step 3 — Calculate Tj and Check Margin
Plug the numbers into the formula above. Then verify:
Tj_margin = Tj_max − Tj_calculated
If the margin is less than 15 °C, you need a bigger heat sink, better airflow, or a lower-loss device.
3. Heat Sink Selection Process
3.1 Determine Required Rth(SA)
Rearrange the junction-temperature equation to solve for the heat sink resistance:
Rth(SA) = (Tj_max − Ta) / P − Rth(JC) − Rth(CS)
Example: A MOSFET dissipating 5 W in a 50 °C ambient, with Tj_max = 150 °C, Rth(JC) = 2 °C/W, and Rth(CS) = 0.5 °C/W:
Rth(SA) = (150 − 50) / 5 − 2 − 0.5 = 20 − 2 − 0.5 = 17.5 °C/W
Any heat sink with Rth(SA) ≤ 17.5 °C/W in the available airflow will keep the junction under 150 °C. To hit a 110 °C design target:
Rth(SA) = (110 − 50) / 5 − 2 − 0.5 = 12 − 2 − 0.5 = 9.5 °C/W
3.2 Heat Sink Sizing Rules of Thumb
- Natural convection: 10–30 °C/W for small clip-on sinks; 2–8 °C/W for larger extruded sinks
- Forced air (3 m/s): 0.5–4 °C/W depending on fin density and size
- Liquid cold plates: 0.05–0.5 °C/W for high-power applications
Always check the manufacturer's curve at your actual airflow velocity, not the "best case" number on the front page.
4. PCB Copper Foil vs. External Heat Sink
For surface-mount power devices (DPAK, D2PAK, QFN with exposed pad), the PCB copper pour is the primary heat sink. The IPC-2152 standard provides guidelines for copper area versus thermal resistance [5].
4.1 PCB Copper as a Heat Sink
A single-layer 1-oz (35 µm) copper pour on FR-4:
| Copper Area (mm²) | Approx. Rth(JA) |
|---|---|
| 100 | 80–100 °C/W |
| 400 | 50–65 °C/W |
| 900 | 35–45 °C/W |
| 1600 | 28–38 °C/W |
| 2500 | 22–32 °C/W |
Moving to 2-oz copper, adding internal planes (2s2p board), or using thermal vias under the exposed pad can cut Rth(JA) by 30–60%.
4.2 When to Switch to an External Heat Sink
| Condition | Recommendation |
|---|---|
| Power < 2 W, SMD device | PCB copper pour is sufficient |
| Power 2–5 W, SMD device | Copper pour + thermal vias to inner plane |
| Power > 5 W, SMD device | External heat sink attached via thermally conductive adhesive or clip |
| Power > 5 W, through-hole (TO-220/TO-247) | Always use external heat sink |
| Power > 20 W | Consider forced air or liquid cooling |
4.3 Thermal Vias
A thermal-via array under an exposed pad transfers heat to inner or bottom-layer planes. Design rules:
- Diameter: 0.2–0.3 mm (small enough to avoid solder wicking)
- Pitch: 0.5–1.0 mm
- Plating: 25 µm minimum copper barrel
- Filled vs. unfilled: Filled+capped vias offer better thermal performance and prevent solder voids, but cost more
A 3×3 via array can reduce Rth(JA) by 15–25% compared to no vias; a 5×5 array can reduce it by 30–40% [5].
5. Thermal Interface Materials: Grease, Pads, and Phase-Change
The Rth(CS) in the thermal chain is dominated by the interface material between the device case and the heat sink. Even two apparently flat metal surfaces touch at only ~2% of their area — the rest is air gaps, and air is a terrible conductor (0.026 W/m·K).
5.1 Thermal Grease
- Typical thermal conductivity: 1–5 W/m·K
- Rth(CS) achieved: 0.2–0.8 °C/W (TO-220)
- Pros: Best thermal performance, fills microscopic voids, low cost
- Cons: Messy application, can dry out over time (pump-out), thickness control is manual
5.2 Thermal Pads (Silicone or Silicone-Free)
- Typical thermal conductivity: 1–6 W/m·K
- Rth(CS) achieved: 0.5–1.5 °C/W (TO-220)
- Pros: Clean, consistent thickness, easy to handle, electrically isolating options available
- Cons: Higher Rth than grease, compression set can loosen over years
5.3 Phase-Change Materials (PCM)
- Typical thermal conductivity: 3–8 W/m·K
- Rth(CS) achieved: 0.3–0.7 °C/W (TO-220)
- Pros: Applies like a pad, flows like grease at operating temperature, no pump-out
- Cons: Higher cost, limited availability
5.4 Best Practices
- Clean both surfaces with isopropyl alcohol before application
- Apply the thinnest practical layer — excess grease does not improve performance
- Use the manufacturer-specified clamping force (typically 10–20 N for TO-220 clips)
- Re-evaluate after thermal cycling — grease pump-out is real for automotive and industrial designs
- For production, prefer pads or PCM for consistency and process control
6. Thermal Simulation Tools
Hand calculations give you a first-order estimate. For production designs, thermal simulation catches hot spots, airflow bypass, and board-level interactions that one-dimensional Rth chains miss.
6.1 Tool Comparison
| Tool | Type | Price | Best For |
|---|---|---|---|
| LTspice (thermal macro) | Circuit simulator | Free | Early design estimation, transient junction temp |
| Simcenter Flotherm | 3D CFD | $$$ | Detailed package + board + enclosure models |
| Ansys Icepak | 3D CFD | $$$ | Electronics enclosures, forced-air and liquid |
| COMSOL Multiphysics | FEM | $$$ | Coupled electro-thermal, custom geometries |
| 6SigmaET | 3D CFD | $$ | Component-level to system-level electronics |
| KiCad + FreeCAD thermal plugins | Open-source | Free | Hobby and low-budget PCB thermal checks |
6.2 Transient Thermal Impedance
Data sheets also provide transient thermal impedance curves (Zth vs. pulse duration). These are critical for pulsed loads — a device can survive far higher peak power than continuous power because the thermal mass of the die and package absorbs short transients.
Zth(t) is always ≤ Rth(steady-state)
For a single pulse of duration t_p:
ΔTj = P_pulse × Zth(t_p)
For repetitive pulses, use the averaged-power approach or the superposition method described in JEDEC JESD51-14 [6].
7. Case Study: 50 W MOSFET Heat Sink Design
Design Requirements
- Device: TO-247 SiC MOSFET (e.g., Wolfspeed C3M0030090K)
- Power dissipation: 50 W
- Ambient temperature: 45 °C (enclosed industrial environment)
- Target Tj: ≤ 125 °C (for 25 °C margin to Tj_max)
- Airflow: 2 m/s forced air
Step 1 — Data Sheet Values
From the C3M0030090K data sheet:
- Rth(JC) = 0.35 °C/W (TO-247, excellent due to SiC die on copper base plate)
- Tj_max = 175 °C
Step 2 — Required Total Thermal Resistance
Rth_total = (Tj_target − Ta) / P = (125 − 45) / 50 = 1.6 °C/W
Rth(SA) = Rth_total − Rth(JC) − Rth(CS) = 1.6 − 0.35 − 0.3 = 0.95 °C/W
We assume Rth(CS) = 0.3 °C/W (good thermal grease, proper clamping force).
Step 3 — Heat Sink Selection
At 2 m/s forced air, we need a heat sink with Rth(SA) ≤ 0.95 °C/W. An extruded aluminum sink approximately 50 × 50 × 25 mm with 30 fins meets this target. A larger folded-fin sink (60 × 60 × 30 mm) gives Rth(SA) ≈ 0.6 °C/W, providing additional margin.
Step 4 — Verification
With the selected heat sink (Rth(SA) = 0.6 °C/W):
Tj = 45 + 50 × (0.35 + 0.3 + 0.6) = 45 + 62.5 = 107.5 °C
Margin to Tj_max: 175 − 107.5 = 67.5 °C ✓
Margin to design target: 125 − 107.5 = 17.5 °C ✓
Step 5 — Transient Check
If the 50 W is a 100 ms pulse (not continuous), the transient impedance Zth(100 ms) might be only 0.4 °C/W instead of the steady-state 1.25 °C/W total:
ΔTj = 50 × 0.4 = 20 °C → Tj = 65 °C
This confirms the design is thermally sound for both continuous and pulsed operation.
Frequently Asked Questions
1. What is the difference between Rth(JA) and Rth(JC)?
Rth(JA) is the total thermal resistance from the silicon junction to ambient air **through the entire package and PCB**, with no external heat sink. Rth(JC) is only the thermal resistance from junction to the **external surface of the package** (the mounting tab or exposed pad). Rth(JA) is used for bare-board designs; Rth(JC) is used when a heat sink is attached, because the heat sink plus interface material provides the remaining thermal path to ambient [1][2].
2. How do I calculate the required heat sink thermal resistance?
Use the rearranged formula: **Rth(SA) = (Tj_max − Ta) / P − Rth(JC) − Rth(CS)**. Set Tj_max to your design target (typically 110–125 °C, not the absolute maximum), Ta to your worst-case ambient, and P to your worst-case power dissipation. The result is the maximum allowable heat-sink-to-ambient thermal resistance. Always choose a heat sink with a lower value to provide safety margin.
3. Can I use PCB copper pour instead of a heat sink for a 5 W MOSFET?
It depends on the package and acceptable Tj. A D2PAK on a 1600 mm² 2-oz copper pour typically achieves Rth(JA) ≈ 30 °C/W. At 5 W in 50 °C ambient: Tj = 50 + 5 × 30 = 200 °C — too hot. You'd need either a much larger copper area (≥2500 mm² with 2-oz copper and thermal vias to an inner plane) or a small clip-on heat sink. A TO-220 on a modest heat sink (Rth(SA) = 10 °C/W) would give Tj = 50 + 5 × (2 + 0.5 + 10) = 107.5 °C, which is comfortable [5].
4. How much does thermal grease improve thermal performance?
Without any interface material (dry contact), Rth(CS) for a TO-220 on a heat sink can be 2–5 °C/W due to microscopic air gaps. A good thermal grease reduces this to 0.2–0.5 °C/W — a 4–10× improvement. For a 10 W device, that's the difference between a 20–50 °C reduction in junction temperature. Always use an interface material; the cost is negligible compared to the thermal benefit [3].
5. What thermal simulation tool should I use for my design?
For early-stage estimation, LTspice's thermal macro model (free) is sufficient. For detailed PCB-level thermal analysis, 6SigmaET or Simcenter Flotherm are industry standards. If you need coupled electro-thermal simulation (e.g., for power IC self-heating), Ansys Icepak or COMSOL Multiphysics are the right tools. For low-budget projects, KiCad with open-source thermal analysis plugins can give approximate board-level results [6].
6. What is transient thermal impedance and when does it matter?
Transient thermal impedance Zth(t) describes the thermal response to a **pulsed** power input. For short pulses (µs to ms), the die's thermal mass absorbs energy without a significant temperature rise, so Zth(t) is much lower than steady-state Rth. This matters in switching converters (pulse loads), motor drives (peak current during acceleration), and pulsed laser drivers. Data sheets provide Zth curves for single pulses; for repetitive pulses, use the superposition method (JEDEC JESD51-14) to calculate the effective junction temperature [6].
References
-
JEDEC JESD51-2, "Integrated Circuits Thermal Test Method Environment Conditions — Natural Convection (Still Air)," JEDEC Solid State Technology Association. https://www.jedec.org/standards-documents/docs/jesd-51-2
-
JEDEC JESD51-12, "Guidelines for Reporting and Using Electronic Package Thermal Information," JEDEC Solid State Technology Association. https://www.jedec.org/standards-documents/docs/jesd51-12
-
S. Lee, "How to Select a Suitable Thermal Interface Material," Electronics Cooling Magazine, 2023. https://www.electronics-cooling.com/
-
Infineon Technologies, "Thermal Resistance Theory and Practice," Application Note AN2015-10, 2015. https://www.infineon.com/dgdl/Infineon-Thermal_resistance_theory_and_practice-AN-v01_00-EN.pdf
-
IPC-2152, "Standard for Determining Current Carrying Capacity in Printed Board Design," IPC International. https://www.ipc.org/TOC/IPC-2152.pdf
-
JEDEC JESD51-14, "Transient Dual Interface Test Method for the Measurement of the Thermal Resistance Junction-to-Case of Semiconductor Devices with Heat Flow Through a Single Path," JEDEC. https://www.jedec.org/standards-documents/docs/jesd51-14
Need power devices with excellent thermal performance? Browse our selection of MOSFETs, IGBTs, and SiC devices at Electronic Component — sourced from leading manufacturers with full data sheets and thermal specifications available for download.