Introduction
Differential signaling has become the backbone of modern high-speed digital communication. From USB 3.x and HDMI to PCIe, DDR4/5 clocks, and Gigabit Ethernet, differential pairs carry the bulk of today's high-speed data. The appeal is clear: by transmitting two equal-and-opposite signals on a tightly coupled pair of traces, differential signaling rejects common-mode noise, doubles signal swing at the receiver, and enables operation at data rates that would be impossible with single-ended signaling.
However, these benefits are only realized when the differential pair is routed correctly. Length mismatches between the positive (D+) and negative (D-) traces introduce intra-pair skew that converts common-mode noise into differential noise, eroding timing margins. Improper spacing between the pair and adjacent signals causes crosstalk that compromises signal integrity. Poor serpentine compensation adds jitter and reflections. Every geometric decision in differential pair routing has electrical consequences that propagate all the way to the system's bit error rate.
This guide covers the complete differential pair routing workflow: signaling fundamentals, length matching tolerances by protocol, intra-pair skew management, gap and spacing rules, serpentine routing techniques, and common-mode considerations. Whether you are routing USB 2.0 at 480 Mbps or PCIe Gen 5 at 32 GT/s, these principles will help you achieve first-pass success.
Differential Signaling Basics
How Differential Signaling Works
A differential driver produces two output signals that are equal in amplitude but opposite in phase. The receiver amplifies the difference between these two signals (V_diff = D+ - D-), rejecting any noise that is common to both inputs. This common-mode rejection is quantified by the Common-Mode Rejection Ratio (CMRR), typically expressed in decibels.
The key advantage is that environmental noise—crosstalk, EMI, power supply ripple—couples equally onto both traces of a tightly coupled pair. Since the receiver subtracts the two signals, this common-mode noise cancels out. The effectiveness of this cancellation depends directly on how symmetrically the pair is routed.
Differential vs. Single-Ended Comparison
| Parameter | Single-Ended | Differential |
|---|---|---|
| Signal swing at receiver | V_swing | 2 × V_swing |
| Noise immunity | Limited by noise margin | High (common-mode rejection) |
| EMI radiation | Higher (unbalanced current) | Lower (fields cancel) |
| Crosstalk susceptibility | High | Low (with tight coupling) |
| Number of traces | 1 per signal | 2 per signal |
| Termination complexity | Simple (single-ended) | More complex (differential + common-mode) |
| Power consumption | Lower | Higher (two drivers) |
| Maximum data rate | ~5–8 Gbps (practical) | 50+ Gbps (PAM4) |
Odd-Mode and Even-Mode Impedance
Each trace in a differential pair has two impedance modes:
- Odd-mode impedance (Z_odd): The impedance of one trace when both traces carry differential signals (equal and opposite). This is lower than the single-ended impedance due to mutual coupling.
- Even-mode impedance (Z_even): The impedance of one trace when both traces carry identical (common-mode) signals. This is higher than the single-ended impedance.
The differential impedance is: Z_diff = 2 × Z_odd
The common-mode impedance is: Z_common = Z_even / 2
Most high-speed protocols specify a differential impedance of 100 Ω (USB, HDMI, Ethernet) or 85 Ω (PCIe). Some legacy interfaces use 90 Ω.
Length Matching Tolerance by Protocol
Why Length Matching Matters
When the D+ and D- traces have different lengths, the differential signal arrives at the receiver with a time skew. This skew has two detrimental effects:
- Timing budget erosion: The skew consumes a portion of the unit interval (UI), reducing the available setup-and-hold window.
- Common-mode conversion: The skew converts a portion of the differential signal energy into common-mode energy, which is not rejected by the receiver and appears as noise.
Protocol-Specific Tolerances
| Protocol | Data Rate | UI (ps) | Max Intra-Pair Skew (ps) | Max Length Mismatch (mils, FR-4) |
|---|---|---|---|---|
| USB 2.0 | 480 Mbps | 2083 | 100 | ~60 |
| USB 3.2 Gen 1 | 5 Gbps | 200 | 15 | ~9 |
| USB 3.2 Gen 2 | 10 Gbps | 100 | 7.5 | ~4.5 |
| HDMI 2.0 | 6 Gbps | 167 | 25 | ~15 |
| HDMI 2.1 | 12 Gbps | 83 | 12 | ~7 |
| PCIe Gen 3 | 8 GT/s | 125 | 12 | ~7 |
| PCIe Gen 4 | 16 GT/s | 62.5 | 6 | ~3.6 |
| PCIe Gen 5 | 32 GT/s | 31.25 | 3 | ~1.8 |
| DDR4 Clock | 3.2 GT/s | 312 | 25 | ~15 |
| 10GBASE-KR | 10.3125 Gbps | 97 | 10 | ~6 |
| 25GBASE-KR | 25.78 Gbps | 38.8 | 4 | ~2.4 |
Practical Length Matching Guidelines
For most protocols, a practical guideline is to match intra-pair lengths within ±5 mils. This is achievable with standard PCB layout tools and provides adequate margin for protocols up to 10 Gbps. For 20+ Gbps protocols, ±2 mils or tighter is necessary, requiring careful serpentine routing and possibly length-matched via transitions.
Intra-Pair Skew Sources
Geometric Length Differences
The most obvious source of intra-pair skew is a physical length difference between the D+ and D- traces. This occurs naturally when routing around obstacles, escaping BGAs, or navigating connector pinouts. The length difference translates directly to a time skew based on the propagation velocity:
Δt = ΔL / v_p
For FR-4 microstrip (v_p ≈ 6 inches/ns), a 5-mil length mismatch produces ~0.83 ps of skew—negligible for USB 2.0 but significant for PCIe Gen 5.
Via Transitions
When a differential pair transitions between layers through vias, the two vias may have different lengths if the transition is not symmetric. This is particularly problematic in thick boards (8+ layers) where the via length can add significant delay. Using blind or buried vias reduces the via stub length and minimizes skew.
Glass Weave Effect
The glass fiber weave in FR-4 and similar laminates creates a periodic variation in dielectric constant. If the two traces of a differential pair fall on different parts of the weave pattern, they experience different effective Dk values, causing skew even when their physical lengths are identical. This "glass weave skew" effect becomes significant above 10 Gbps and is mitigated by:
- Routing traces at an angle (10°–15°) to the weave
- Using spread-glass or glass-free laminates (e.g., Megtron 6, Tachyon 100G)
- Rotating the layout artwork relative to the panel
Gap and Spacing Control
Intra-Pair Gap
The gap between the two traces of a differential pair (intra-pair spacing) affects both the differential impedance and the coupling strength. A smaller gap increases coupling, which:
- Lowers differential impedance (requiring narrower traces to compensate)
- Improves common-mode noise rejection
- Reduces EMI radiation
- Makes the pair more susceptible to fabrication variations
Common guidelines for intra-pair gap:
| Gap (× trace width) | Coupling Strength | Differential Impedance Change | Typical Application |
|---|---|---|---|
| 0.5× (tightly coupled) | Strong | -15% vs. uncoupled | PCIe, high-speed serial |
| 1.0× (moderately coupled) | Moderate | -8% vs. uncoupled | USB, HDMI, Ethernet |
| 2.0× (loosely coupled) | Weak | -3% vs. uncoupled | Lower-speed differential |
| 3.0×+ (uncoupled) | Negligible | Baseline | Not recommended for differential |
Inter-Pair Spacing
The spacing between different differential pairs must be large enough to prevent pair-to-pair crosstalk. The recommended minimum is:
- 5W rule: 5× trace width between pair edges for standard-speed differential pairs
- 7W–10W rule: For multi-gigabit serial links, especially when pairs run parallel for extended distances
- 30 mils minimum: An absolute floor for high-speed differential pairs, regardless of trace width
Routing to Connectors
Connector pinouts often force differential pairs to spread apart or change direction near the pads. This region is a common source of impedance discontinuities. Best practices include:
- Maintain the designed gap as close to the connector pads as possible
- Use teardrop or rounded pad entries to minimize capacitance
- Match the pad size to the trace width to minimize impedance bumps
- If the gap must increase near the connector, use a gradual transition (no sudden changes)
Serpentine Routing for Length Matching
How Serpentine Routing Works
Serpentine routing (also called accordion routing) adds extra trace length to the shorter trace of a differential pair by routing it in a zigzag pattern. This compensates for length differences caused by BGA escape, connector routing, or obstacle avoidance.
The added length from a serpentine section is:
ΔL = N × 2 × A
where N is the number of serpentine bumps and A is the amplitude of each bump.
Serpentine Design Rules
Poorly designed serpentines can introduce more problems than they solve. Key rules:
- Minimum serpentine gap: The gap between adjacent serpentine segments should be at least 3× the trace width (same as the 3W rule) to prevent self-crosstalk within the serpentine.
- Maximum serpentine amplitude: Keep the serpentine amplitude small to minimize the area where the trace deviates from the straight-line path. Large amplitudes create large impedance discontinuities.
- Place serpentines away from the receiver: Ideally, place serpentine compensation in the middle of the trace, not near the driver or receiver. This minimizes the impact of any residual reflections.
- Avoid multiple serpentine clusters: If significant compensation is needed, use one continuous serpentine section rather than multiple small ones scattered along the route.
- Match serpentine geometry on both traces: If one trace has serpentine routing, adding a small matching serpentine to the other trace (even if not needed for length) can help equalize impedance effects.
Serpentine vs. Trombone Routing
| Feature | Serpentine (Accordion) | Trombone (S-Curve) |
|---|---|---|
| Shape | Repeated zigzag pattern | Single S-curve |
| Length compensation | Small to large amounts | Small amounts |
| Space efficiency | High (compact) | Low (requires width) |
| Self-crosstalk risk | Higher (parallel segments) | Lower |
| Impedance discontinuity | Multiple small bumps | One moderate bump |
| Best for | Dense BGA escape areas | Open routing areas, small corrections |
Common-Mode Considerations
Common-Mode Signal Generation
Even with perfectly matched lengths, differential pairs can carry common-mode signals generated by:
- Driver asymmetry (unequal rise/fall times)
- Power supply noise coupling equally to both outputs
- Ground bounce at the driver
- Impedance discontinuities that are common to both traces
Common-Mode Termination
Some high-speed protocols require common-mode termination in addition to differential termination. The most common approach is the "pi" termination network: two resistors (each 2 × Z_odd = Z_even) connected from each trace to a common node, which is then bypassed to ground with a capacitor.
For a 100 Ω differential pair (Z_odd = 50 Ω), the pi termination uses two 100 Ω resistors to a common node, with a 100 nF capacitor to ground. This terminates both differential (100 Ω) and common-mode (50 Ω) signals.
Common-Mode Chokes
For applications where common-mode noise must be minimized—such as USB, HDMI, and Ethernet—common-mode chokes (CMC) are placed in series with the differential pair. A CMC presents high impedance to common-mode signals while passing differential signals with minimal attenuation. Selecting a CMC with appropriate impedance vs. frequency characteristics is critical:
- The differential insertion loss should be < 1 dB up to the Nyquist frequency
- The common-mode attenuation should be > 20 dB in the noise band of interest
- The rated current must exceed the differential signal current
Protocol-Specific Routing Tips
USB Routing
- USB 2.0: 90 Ω differential impedance, ±150 mils length matching. Route on a single layer if possible; avoid layer transitions.
- USB 3.x: 90 Ω differential impedance for both TX and RX pairs. ±5 mils length matching. Route TX and RX pairs with at least 5W separation. Use AC coupling capacitors (0.1 μF) on TX pairs.
HDMI Routing
- Four shielded differential pairs (TMDS Clock, Data 0, Data 1, Data 2) plus additional signals
- 100 Ω differential impedance
- ±15 mils intra-pair length matching for HDMI 2.0; ±7 mils for HDMI 2.1
- Route all four pairs on the same layer with identical geometry
- Use ground shielding between pairs (ground trace or copper pour with vias)
PCIe Routing
- 85 Ω differential impedance (check device specification—some use 100 Ω)
- TX and RX pairs are AC coupled (0.1 μF or 0.22 μF capacitors)
- Length matching: ±5 mils for Gen 3, ±2 mils for Gen 4/5
- Route TX and RX on separate layers if possible to minimize crosstalk
- Add ground guard vias near AC coupling capacitors
