PCB stackup design: how we engineer a lower-risk path for AI and data-center servers PCBA

Written by Informic Engineering Team. Technical claims require documented source review before publication.

When we sit down with a design team building a server board for AI inference or data-center workloads, the first question is rarely about component count. It is about the stackup. The layer count, the dielectric materials, the copper weights, and the impedance plan determine whether that board will route cleanly, assemble without warpage, and perform at 112G or 224G SerDes speeds. We are going to walk through the engineering checklist we use daily when reviewing stackups for high-layer-count PCBs, and how that review connects directly to BOM sourcing and consolidation.

Our direct answer: a lower-risk path for AI and data-center server PCBA starts with a stackup that is manufacturable, testable, and sourceable. If the stackup forces exotic materials or non-standard drill sizes, you will pay for it in lead time and yield. We design for the fab’s capability, not for the datasheet’s maximum.

Start with the signal integrity budget, not the layer count

We see teams specify 24 or 30 layers because they think more layers equal better performance. That is not always true. The real constraint is the dielectric thickness between reference planes and the copper roughness at the frequencies you care about. For 112G PAM4, the insertion loss budget is tight. A standard FR4 with a Dk of 4.2 and a dissipation factor of 0.020 will not work for long traces. You need a mid-loss or low-loss laminate, but only on the layers that carry high-speed signals.

Technical reference: For related engineering context, see IPC standards and industry resources.

Ask yourself: which nets actually need the low-loss material? PCIe Gen5, 400G Ethernet, and DDR5 interfaces have different requirements. A hybrid stackup. using a low-loss material for the outer signal layers and a standard FR4 for the power and ground planes. can save 15-20% in material cost without sacrificing performance. We recommend that every design team produce a loss budget table before finalizing the stackup. If you cannot quantify the insertion loss per inch for each high-speed net, you are guessing.

Here is the practical checklist we use when reviewing a stackup for an AI server board:

• Define the maximum trace length for each high-speed interface and calculate the allowed loss per inch.
• Select the laminate grade based on the worst-case loss budget, not the average.
• Specify copper roughness (RT) values. smooth copper for high-speed layers, standard for power.
• Verify the glass weave style to minimize skew on differential pairs.
• Confirm the prepreg build-up will not create resin-starved areas near blind vias.

Layer count and routing density: a cost-driver analysis

We often review stackups where the design team has added two extra layers just to route a few signals. That is a BOM and manufacturing risk. Each additional layer adds material cost, drilling time, lamination cycles, and potential for warpage. For a data-center server board that measures 18x24 inches, a 20-layer stackup might cost 30% more than a 16-layer board, but the routing density may not justify it.

Use a simple rule: if you have fewer than 200 nets per square inch, you likely do not need more than 16 layers. AI accelerators with high pin-count packages may need 24, but that is rare. We always ask for a net density map before approving a stackup. If the map shows large empty areas, we suggest reducing layer count and using microvias to break out the BGA.

The table below summarizes the trade-offs we see in typical server stackups:

We are not saying avoid high layer counts. We are saying justify them with a routing analysis. If you cannot show that a 22-layer board is necessary for signal integrity, you are adding cost and lead time without benefit.

Material selection: balancing Dk, Df, and availability

Material selection is where we see the most BOM risk. A design might specify a particular low-loss laminate that has a 12-week lead time, while a comparable material from another supplier is in stock. For a data-center server program, that difference can delay the entire product launch.

We recommend specifying materials by performance class, not by brand. For example, instead of writing "MEGTRON6" on the drawing, write "low-loss laminate with Dk 3.4-3.6 and Df ≤ 0.005 at 10 GHz." That allows the fab to offer an equivalent material that is available. You still get the electrical performance, but you avoid a sole-source situation.

When we review a stackup, we check the material against our components sourcing database. If a material is on allocation, we flag it early. The same applies to copper foils. reverse-treated foil is common for high-speed, but it has longer lead times than standard ED foil. If your stackup uses RT foil on all layers, you may be creating a bottleneck.

Here is the material checklist we use:

• Confirm the Dk and Df values at your operating frequency, not at 1 GHz.
• Check the glass transition temperature (Tg) for lead-free assembly. 170°C or higher is typical.
• Verify the CTE (coefficient of thermal expansion) in the Z-axis to avoid via cracking.
• Ask for the material’s moisture absorption rate. high absorption affects impedance.
• Request a second-source equivalent from the fab before you finalize the drawing.

Impedance control and manufacturing tolerances

For 85-ohm differential pairs on a server board, the tolerance is usually ±10%. But that tolerance is measured after etching, and the etch factor varies with copper weight and line width. We always ask the fab for their etch compensation model before we approve a stackup. If the fab cannot hold ±5% on the inner layers, you will have impedance failures on the test bed.

A practical step is to design the stackup with a slightly wider trace than the nominal calculation. For example, if the calculator says 4.5 mils, design for 4.8 mils. That gives you margin for etch variation. We also recommend adding coupon test points on every signal layer, not only the outer layers. This allows the fab to verify impedance during production, not after the board is assembled.

Another area we focus on is the reference plane. If you have a signal layer adjacent to a plane that is split for different voltages, you will get return path discontinuity. We ask design teams to keep the reference plane intact for at least 20 mils on either side of the trace. If that is not possible, you need to add stitching vias every 100 mils.

Via structure and drill size: the hidden BOM cost

Blind and buried vias are necessary for high-density boards, but they add significant cost. A standard through-hole via costs fractions of a cent, while a laser-drilled microvia can cost several cents. On a board with 10,000 vias, that difference adds up quickly. We recommend using a staggered via design instead of stacked vias when possible. Staggered vias are easier to drill and plate, and they have a lower failure rate.

Drill size is another factor. A 0.2mm mechanical drill is common, but 0.15mm requires specialized equipment and has a higher breakage rate. We always ask: can you route this signal on an outer layer instead of using a blind via? If yes, do that. The stackup should minimize the number of via transitions for high-speed nets, but it should also minimize the total via count for cost.

When we review a stackup, we count the via types and estimate the drilling time. If the stackup has more than three via types, we ask for simplification. The fab’s drilling cycle time directly affects your lead time, and lead time affects your ability to meet a launch date.

Warpage and assembly yield: the mechanical side

AI server boards are large and heavy. A 24-layer board with 2oz copper on the outer layers can warp during reflow if the stackup is not symmetric. We always check the copper balance on each layer pair. If one side has 70% copper and the other has 30%, the board will bow. We recommend keeping the copper density within 10% between adjacent layers.

Another mechanical concern is the panel size. A 24x18 inch board will use a full panel, but the fab may have a maximum panel size of 21x24. We verify the panel utilization early. If the board does not fit efficiently on a standard panel, the cost per board increases by 15-20%.

We also check the solder mask type. For server boards, a liquid photoimageable (LPI) mask is standard, but it has a thickness variation that affects impedance on the outer layers. If you need tight impedance control, consider a dry film mask. It is more expensive but provides a more uniform thickness.

Here is the mechanical checklist we apply:

• Verify copper balance per layer pair (within 10%).
• Confirm the board thickness is within the fab’s aspect ratio limit for drilling.
• Check the solder mask thickness on high-speed outer layers.
• Specify a surface finish that matches the assembly process. ENIG is common, but ENEPIG may be needed for wire bonding.

Connecting stackup design to BOM sourcing

We view the stackup as the first item in the BOM. If the stackup is wrong, every component on the board is at risk. That is why we work with the procurement team to source the laminate and copper foil early. For a typical server board, the bare PCB can be 30-40% of the total BOM cost. Getting that right is critical.

When we help a customer with BOM consolidation, we start by reviewing the stackup against our pcbManufacturing capabilities. We then cross-reference the components with our pcba assembly partners. This allows us to identify potential supply chain issues before the design is frozen.

For example, if a design specifies a 0.5mm pitch BGA that requires a microvia-in-pad, we check that the fab can handle the via fill and plating. If not, we suggest a 0.65mm pitch package that is more manufacturable. This is not a compromise. it is a risk mitigation.

Practical steps for your next design review

We recommend that every design team create a stackup review document that includes the following:

1. A loss budget table for each high-speed interface.
2. A net density map showing routing congestion.
3. A via count and type summary.
4. A material specification by performance class, not brand.
5. A copper balance chart per layer.

If you have these five items, you can have a productive conversation with your fab and your component supplier. Without them, you are asking for quotes on a moving target.

When you are ready to move from design to production, we encourage you to quote your stackup with us. We will review it for manufacturability and provide a BOM sourcing plan that reduces lead time and cost.

Below are three images that illustrate the key concepts we have discussed.

FAQ: PCB stackup design for AI and data-center servers

What is the most common mistake in PCB stackup design for server boards?

We see over-specification of materials. Teams specify low-loss laminate on all layers, even where it is not needed. This increases cost and lead time. Use a hybrid stackup. low-loss material only on high-speed signal layers, standard FR4 for power and ground.

How do I choose between a 16-layer and 20-layer stackup?

Start with a net density map. If you have fewer than 200 nets per square inch, 16 layers is likely enough. If you have high pin-count ASICs or FPGAs with dense breakout, you may need 20 or more. Always verify with a routing study before committing to a layer count.

Should I specify a specific laminate brand on my drawing?

No. Specify the electrical performance parameters. Dk, Df, Tg, and CTE. This allows the fab to offer an equivalent material that is in stock. Brand-specific specifications create sole-source situations that delay production.

FAQ

Sources

1. IPC Introduction to PCB Design for Manufacturability
2. TI Final Test Considerations for Wireless Technology Products
3. IPC Board Design Standards