Keywords: AEC-Q100, automotive IC certification, car-grade chip qualification, AEC-Q100 test
What Is AEC-Q100?
AEC-Q100 is the Automotive Electronics Council's stress-test qualification standard for integrated circuits (ICs) used in automotive applications. First released in 1994 and updated multiple times (Rev H is the current major revision), it defines a rigorous suite of stress tests that a semiconductor device must pass before it can be labeled "automotive-grade" or "car-grade."
The standard exists because automotive electronics operate in environments far harsher than consumer electronics: temperature swings from −40 °C to +150 °C, constant vibration, humidity, chemical exposure, and 15-year expected service life with near-zero field failure rates. AEC-Q100 certification is the industry's way of proving a chip can survive all of that [1].
If you manufacture or source ICs for automotive use — whether for engine control units (ECUs), advanced driver-assistance systems (ADAS), infotainment, or battery management systems (BMS) — AEC-Q100 is not optional. It is the baseline gate.
Temperature Grades: 0 Through 3
AEC-Q100 classifies devices into four temperature grades. The grade you target determines the severity of every downstream test.
| Grade | Ambient Temp Range | Typical Application |
| Grade 0 | −40 °C to +150 °C | Engine compartment, transmission, exhaust-adjacent sensors |
| Grade 1 | −40 °C to +125 °C | Under-hood modules, powertrain ECUs |
| Grade 2 | −40 °C to +105 °C | Cabin-adjacent electronics, door modules |
| Grade 3 | −40 °C to +85 °C | Interior electronics, infotainment, climate control |
Grade 0 is the most demanding. A device qualified to Grade 0 automatically satisfies Grade 1–3 requirements, but the reverse is not true. Most automotive-grade MCUs and power ICs on the market today target Grade 1, which covers the majority of under-hood applications [2].
The Core Test Categories
AEC-Q100 is not a single test — it is a matrix of more than 20 stress tests organized into families. Below are the critical ones every automotive IC must undergo.
1. Temperature Cycling (TC)
Purpose: Simulate the mechanical stress caused by repeated thermal expansion and contraction.
Devices are cycled between extreme cold (−65 °C) and extreme hot (+150 °C) with rapid transitions. The standard requires 500 to 5,000 cycles depending on the grade and package type. This test exposes die-attach fatigue, wire-bond failures, and solder joint cracking.
2. High-Temperature Operating Life (HTOL / HTRB)
Purpose: Validate long-term reliability under worst-case operating conditions.
Also called High-Temperature Reverse Bias (HTRB) for discrete devices, this test runs the device at maximum rated voltage and temperature (typically 125 °C or 150 °C) for 1,000 to 2,000 hours. It accelerates failure mechanisms like dielectric breakdown, electromigration, and ionic contamination.
3. High-Temperature Gate Bias (HTGB)
Purpose: Stress the gate oxide of MOSFETs and IGBTs at elevated temperature.
The gate is biased at maximum rated VGS while the drain is left open, held at 150 °C for up to 1,000 hours. This test catches gate-oxide defects, mobile-ion contamination, and threshold-voltage shifts — failure modes specific to power devices [3].
4. Highly Accelerated Stress Test (HAST)
Purpose: Combine temperature, humidity, and pressure to accelerate corrosion and moisture ingress.
Conditions: 130 °C, 85% relative humidity, 2.3 atm pressure, for 96 to 264 hours. HAST is the modern replacement for the older 85/85 test (THB), delivering the same failure mechanisms in a fraction of the time. It exposes epoxy delamination, aluminum pad corrosion, and wire-bond degradation.
5. Unbiased HAST (UHAST)
Purpose: Same environment as HAST but without electrical bias.
UHAST isolates moisture-driven failure mechanisms from voltage-driven ones. It is particularly relevant for plastic-encapsulated devices where moisture absorption is the primary concern.
6. Power Temperature Cycling (PTC)
Purpose: Simulate thermal stress from self-heating during power-on/power-off cycles.
Unlike TC (which uses external chamber heating), PTC cycles the device's internal power dissipation to create thermal gradients. This is critical for power ICs and MOSFETs where junction temperature swings dramatically during operation. Typical requirement: 5,000 to 15,000 cycles.
7. Electrostatic Discharge (ESD)
Purpose: Verify the device survives real-world ESD events.
Two models are required: - HBM (Human Body Model): Simulates discharge from a charged person touching a pin. Typical pass level: ±2,000 V (Class 2) or ±8,000 V (Class 3A). - CDM (Charged Device Model): Simulates a charged package discharging to a grounded surface. Increasingly the dominant real-world ESD failure mode. Typical pass level: ±750 V to ±1,500 V.
8. Latch-Up (LU)
Purpose: Confirm the device does not enter a destructive parasitic thyristor conduction state.
A current injection test per JEDEC JESD78. The device must survive ±100 mA injection at maximum operating temperature without latch-up. This is a design-rule check as much as a reliability test — if a device fails latch-up, it usually requires a silicon-level redesign.
Additional Test Requirements
Beyond the eight core tests above, AEC-Q100 mandates several additional checks depending on device type and package:
- Pre- and Post-Stress Electrical Testing: Every unit is electrically tested before and after each stress test. Drift limits are defined in the device specification. - Physical/Dimensional Inspection: Package dimensions, lead coplanarity, and marking durability. - Solderability (per J-STD-002): Validates the terminations can be reliably soldered in a Pb-free reflow process. - Flammability (UL 94 V-0): Mold compound must meet V-0 flame rating. - Wire Bond Integrity: Ball shear and wire pull tests per AEC-Q100 Table 6.
The full test list varies by device family (Table 5 in the standard). For example, memory devices have additional retention and cycling tests; sensors have mechanical shock and variable frequency vibration tests.
Certification Timeline: 6 to 12 Months
A full AEC-Q100 qualification campaign is not a sprint. A realistic timeline:
| Phase | Duration | Activities |
| Test Plan Definition | 2–4 weeks | Failure Mode Effects Analysis (FMEA), grade selection, test sample planning |
| Test Vehicle Fabrication | 8–12 weeks | Qualification lots built with production-intent design and materials |
| Stress Testing Execution | 12–24 weeks | All tests run in parallel where possible; HTOL is usually the longest pole |
| Data Analysis & Report | 2–4 weeks | Statistical analysis, delta calculations, qualification report |
| Audit & Approval | 2–4 weeks | Customer or third-party review of the qualification report |
Total: 6–12 months from test plan to signed-off qualification report, assuming no failures. If a device fails a stress test mid-stream, expect to add 3–6 months for root-cause analysis, design or process fix, and re-test [4].
Cost Considerations
AEC-Q100 qualification is expensive. Typical cost breakdown for a mid-complexity IC (e.g., a 32-bit MCU in a QFP package):
- Qualification lots: $50,000–$150,000 (2–3 wafer lots, not salable) - Third-party test lab fees: $30,000–$80,000 (all stress tests + electrical characterization) - Engineering labor: $40,000–$100,000 (test plan, data analysis, report) - Packaging & assembly: $10,000–$30,000 (special build for qual units) - Re-test reserve (if first attempt fails): 30–50% of the above
Total estimate: $130,000–$360,000 for a single device/package/grade combination.
This is why semiconductor companies amortize qualification costs across high-volume automotive programs. Qualifying a device for a low-volume niche application may be economically infeasible.
Automotive-Grade vs. Industrial-Grade: What's Different?
A common question from design engineers: *Can I use an industrial-grade IC in a non-critical automotive module?* The short answer is no, not if the module is subject to automotive qualification requirements. Here is why:
| Parameter | AEC-Q100 (Automotive) | Industrial / Commercial |
| Temperature Range | −40 to +150 °C (Grade 0) | −40 to +85 °C or −40 to +125 °C |
| Operating Life | 15+ years, near-zero ppm | 3–5 years, ~100 ppm acceptable |
| HTOL Duration | 1,000–2,000 hours | 500–1,000 hours (typical) |
| Temperature Cycling | 500–5,000 cycles | 200–500 cycles |
| HAST | Required | Often not required |
| Latch-Up | Required (JESD78) | Not always required |
| Traceability | Wafer-level lot traceability | Lot-level only |
| PPAP | Required for automotive | Not required |
| Failure Rate Target | ≤1 ppm over service life | ≤100 ppm acceptable |
The gap is not just in test severity. Automotive-grade devices require full traceability from wafer to finished unit, adherence to IATF 16949 quality management systems, and Production Part Approval Process (PPAP) submissions for every manufacturing change. An industrial-grade IC might pass the same silicon design, but without the documentation, traceability, and process controls, it cannot be used in safety-relevant automotive systems [5].
Common Failure Modes in AEC-Q100 Testing
Understanding why devices fail helps designers avoid the same traps. Based on industry data from major automotive OEMs and Tier 1 suppliers:
1. Temperature Cycling Failures (most common, ~35% of all failures)
- Die-attach delamination due to CTE mismatch between silicon, die-attach material, and lead frame - Wire-bond heel cracking from repeated flexure - Solder joint fatigue in BGA packages
2. HTOL Failures (~25%)
- Electromigration in narrow metal traces at high current density - Gate-oxide breakdown in sub-100nm nodes - Hot-carrier injection degradation in analog circuits
3. HAST / UHAST Failures (~15%)
- Moisture ingress through mold compound → aluminum pad corrosion - Popcorning during reflow (moisture-induced package cracking) - Delamination at die-to-mold compound interface
4. ESD Failures (~10%)
- Insufficient on-chip ESD protection cells - CDM failures due to thin gate oxide in advanced nodes - Inadequate grounding in multi-domain power ICs
5. Latch-Up Failures (~5%)
- Insufficient guard rings in I/O cells - Minority carrier injection from power pins into substrate - Often a design oversight caught too late
The remaining ~10% includes mechanical shock, vibration, and miscellaneous failures.
Frequently Asked Questions
Q1: Is AEC-Q100 certification mandatory for all automotive ICs?
Legally, no — there is no law requiring AEC-Q100. However, virtually every major automaker and Tier 1 supplier specifies AEC-Q100-qualified components in their design requirements. If your IC is not certified, it will not be designed into automotive programs. For safety-relevant systems (ISO 26262 ASIL-rated), AEC-Q100 is a prerequisite, not a substitute — you need both.
Q2: How long is an AEC-Q100 qualification valid?
Qualification is valid as long as the device is manufactured with no changes to the design, wafer process, package, or assembly site. Any change — even a die-shrink or a mold-compound supplier switch — triggers a re-qualification or delta-qualification. Most companies maintain a change-control system to track this. The qualification report itself does not expire, but automakers may request periodic re-test data (e.g., annual HTOL surveillance).
Q3: What's the difference between AEC-Q100 and AEC-Q200?
AEC-Q100 covers integrated circuits (semiconductor devices with active circuitry — MCUs, power ICs, memories, sensors with on-chip electronics). AEC-Q200 covers passive components (resistors, capacitors, inductors, transformers). If you are qualifying a discrete transistor, AEC-Q101 applies. For optoelectronics, it's AEC-Q102. Each standard has its own test matrix tailored to the failure modes of that component class.
Q4: Can I use a Grade 1 device in a Grade 0 application?
No. A Grade 1 device is only qualified to +125 °C ambient. If your application sees junction temperatures above 125 °C (e.g., engine-mounted sensors, exhaust-area modules), you need a Grade 0-qualified device. Using a lower grade in a higher-temperature environment voids the qualification and creates field-failure risk. The only exception is if you do your own additional qualification to Grade 0 conditions — but this is rare and usually not accepted by OEMs without full AEC-Q100 Grade 0 documentation.
Q5: Does AEC-Q100 apply to semiconductor manufacturing processes or just the final device?
AEC-Q100 qualifies the final packaged device, not the wafer process in isolation. However, the standard requires that qualification lots be built using the production-intent wafer process, package, and assembly flow. This means process changes (e.g., migrating from 28nm to 16nm, or changing the wafer foundry) require re-qualification. The standard also references JEDEC JESD47 (test guideline for semiconductor devices) for process-level reliability.
Q6: How many samples are needed for AEC-Q100 testing?
Sample sizes are defined in AEC-Q100 Table 4 and vary by test type and device complexity. Typical requirements: HTOL — 3 lots × 77 units (231 total); Temperature Cycling — 3 lots × 33 units (99 total); HAST — 3 lots × 25 units (75 total); ESD — 3 parts per stress level minimum. These sample sizes are based on LTPD (Lot Tolerance Percent Defective) sampling plans, targeting ~90% confidence of detecting failures at defined defect rates.
Conclusion
AEC-Q100 certification is the gold standard for automotive IC reliability — and for good reason. The combination of extreme environmental stress testing, stringent sample sizes, and mandatory documentation creates a qualification bar that genuinely separates automotive-grade silicon from the rest.
For IC manufacturers, the path to certification is well-defined but expensive: 6–12 months, $130K–$360K per device, and zero tolerance for failure on the first attempt. For automotive designers and procurement engineers, specifying AEC-Q100-qualified components is the single most effective way to minimize field-failure risk over a 15-year vehicle service life.
The key takeaway: AEC-Q100 is not a checkbox. It is a comprehensive system-level qualification that validates the device, the package, the process, and the production chain — all of which must remain unchanged for the certified device to remain certified.
References & External Links
[1] Automotive Electronics Council — AEC-Q100 Rev H Stress Test Qualification for Integrated Circuits https://www.aecouncil.com/AECDocuments.html
[2] JEDEC JESD47 — Test Guideline for Semiconductor Devices (referenced by AEC-Q100) https://www.jedec.org/standards-documents/docs/jesd-47
[3] Infineon Technologies — Automotive Power Device Qualification White Paper https://www.infineon.com/dgdl/Infineon-Automotive_power_device_qualification-Whitepaper-v01_00-EN.pdf
[4] KEMET Electronics — AEC-Q200 and AEC-Q100 Qualification Overview https://www.kemet.com/en/us/technical-resources/automotive-qualifications.html
[5] Texas Instruments — Automotive-Grade IC Qualification and IATF 16949 https://www.ti.com/quality-reliability-packaging/quality-reliability/automotive-qualified-products.html
*This article is for informational purposes and reflects industry-standard practices as of 2026. Always consult the latest AEC-Q100 revision and your customer's specific qualification requirements before beginning a certification campaign.*