High-Speed Differential Pair Routing: USB 3.0 and HDMI 90Ω/100Ω Design Guide

When you're routing USB 3.0 SuperSpeed at 5 Gbps or HDMI at 340 MHz pixel clock, the margin for error in your differential pairs shrinks dramatically. A single split-plane crossing, an unmatched via, or 5 mils of length skew can turn a clean eye diagram into a disaster. This guide walks through the practical rules for designing 90Ω and 100Ω differential pairs that pass compliance testing on the first try.

Why Differential Signaling Demands Precision

Differential signaling transmits two complementary signals (D+ and D−) along matched traces. The receiver decodes the voltage *difference* between them, which cancels common-mode noise. But this noise rejection only works when both traces experience identical interference — meaning they must be routed in parallel, at the same length, over the same reference plane.

At USB 3.0's 5 Gbps data rate, a bit period is just 200 ps. A length mismatch of just 3 mils (≈0.076 mm) introduces roughly 1.1 ps of skew — small, but it accumulates fast across multiple mismatches. At HDMI's TMDS rates, similar constraints apply [1].

Core Differential Pair Routing Rules

1. Parallel Routing with Controlled Spacing

The two traces in a differential pair must run parallel with a consistent gap between them. This gap, combined with trace width and dielectric thickness, determines the differential impedance.

Key spacing rules:

Intra-pair gap: Typically 3× to 5× the trace width for edge-coupled microstrip, or per your stackup simulation

Inter-pair spacing: Minimum 5× the trace width (or 3× the intra-pair gap) to minimize crosstalk between pairs

Keep the gap constant: Any change in spacing creates an impedance discontinuity and mode conversion

For USB 3.0 (90Ω differential), a common stackup might use 4-mil traces with 4-mil spacing on a 4-mil dielectric over a ground plane. For HDMI (100Ω differential), tighter spacing or thinner dielectric may be needed [2].

2. Length Matching — The Non-Negotiable Rule

Both traces in a pair must arrive at the receiver at the same time. Length mismatch causes intra-pair skew, which directly degrades the eye diagram.

Tolerances by standard:

Standard	Max Intra-Pair Skew	Max Length Mismatch
USB 3.0 SuperSpeed	5 ps	≈0.7 mm (28 mils)
USB 2.0 High-Speed	50 ps	≈7 mm
HDMI TMDS	10 ps	≈1.5 mm (60 mils)
PCIe Gen 3	2 ps	≈0.3 mm (12 mils)

When bends cause length differences (a 90° corner adds extra length to the outer trace), you must compensate.

3. Serpentine Length Matching

Serpentine (accordion) routing is the standard technique to equalize trace lengths. The shorter trace gets a series of small bumps to add the missing length.

Serpentine best practices:

Place compensations near the mismatch source. If a bend creates 2 mils of skew, add the serpentine immediately after that bend — not 500 mils downstream

Keep amplitude small: Use 2–3× trace width for the serpentine bump height

Minimize the serpentine section length: Only add what's needed to match

Avoid serpentine in high-coupling regions: The bumps locally reduce coupling, creating impedance dips

A common mistake is adding all compensation at the end of the trace. This leaves a long section of unmatched skew, allowing noise to affect each trace differently before compensation occurs [3].

4. Reference Plane Continuity

This is the single most common failure mode in differential pair routing. The signal return current flows in the reference plane directly beneath the traces. If that plane is interrupted — by a split, a void, or a layer change — the return path is broken.

What happens when the return path breaks:

Return current takes a detour through parasitic capacitance and inductance

Impedance spikes to 150Ω+ at the discontinuity

Signal reflections increase dramatically

EMI radiation jumps 10–20 dB

Mode conversion (differential-to-common) degrades the eye

Rules:

Never route a differential pair across a split in the reference plane

If a plane split is unavoidable, add stitching capacitors (0.1 µF) across the split to provide an AC return path

Keep the reference plane solid for the entire trace length

If changing layers, place ground vias adjacent to signal vias to provide a return path

5. Via Minimization and Layer Transitions

Every via adds parasitic capacitance (typically 0.3–0.5 pF) and inductance (0.5–1 nH) to the trace. In differential pairs, if one trace goes through a via and the other doesn't, you've created a massive impedance discontinuity.

Via rules for differential pairs:

Minimize layer transitions: Route the entire pair on one layer if possible

If vias are necessary, use both: Both traces must transition layers at the same location

Match via count: If one trace has 2 vias, the other must have 2 vias — no exceptions

Use blind/buried vias when possible: Shorter via stubs reduce reflections

Back-drill (controlled depth) vias for multi-Gbps signals to eliminate stub effects

Place ground vias near signal vias: Within 3× the via antipad diameter for return current continuity

USB 3.0 SuperSpeed: 90Ω Differential Implementation

USB 3.0 SuperSpeed (5 Gbps) uses 90Ω differential impedance with AC coupling capacitors (75–200 nF) on the TX lines. The SuperSpeed pairs are:

TX+ / TX− (host to device transmit)

RX+ / RX− (device to host receive)

USB 3.0-specific routing requirements:

Differential impedance: 90Ω ±7% (83–97Ω) per the USB 3.0 specification

Single-ended impedance: 45Ω ±10% per trace

Intra-pair skew: Maximum 5 ps

AC coupling caps: Place on TX lines only, close to the host connector. Use small package (0402 or 0201) to minimize pad discontinuity

Connector routing: Maintain differential impedance through the connector breakout region. Use short stubs to the connector pads

Crosstalk: Maintain minimum 3× trace width separation between TX and RX pairs

No 90° corners: Use two 45° bends or curved corners instead

The USB 3.0 spec also requires compliance testing using a eye diagram mask test at 5 Gbps. Your layout must produce an eye that fits within the defined mask with margin to spare [4].

HDMI: 100Ω Differential Implementation

HDMI uses Transition Minimized Differential Signaling (TMDS) with four differential pairs (three data + one clock), each at 100Ω differential impedance.

HDMI-specific routing requirements:

Differential impedance: 100Ω ±10% (90–110Ω)

Single-ended impedance: 50Ω ±10%

Intra-pair skew: Maximum 10 ps per pair

Inter-pair skew: Clock-to-data skew must be controlled within ±0.15 × T_pixel

Trace width/spacing: Typically 5/5 mil (width/gap) on standard 4-layer FR-4, but always simulate your stackup

ESD protection diodes: Place close to the HDMI connector. Account for their parasitic capacitance in impedance calculations

No stubs: Even short stubs on TMDS lines cause reflections at GHz frequencies

Pair-to-pair spacing: Minimum 4× trace width between adjacent TMDS pairs

Eye Diagram Testing and Signal Integrity

The eye diagram is the ultimate pass/fail test for differential signal integrity. It overlays all bit transitions on top of each other, creating an "eye" shape. A clean, open eye means your signal has good margin; a closed or distorted eye means problems.

What the Eye Diagram Tells You

Eye height: Voltage margin — reduced by attenuation, reflections, and noise

Eye width: Timing margin — reduced by jitter, skew, and ISI (inter-symbol interference)

Rise/fall time: Should be sharp and symmetrical

Overshoot/undershoot: Indicates impedance mismatches

Common Eye Diagram Failures

Problem: Eye is too narrow (timing closure)

Cause: Excessive intra-pair skew, jitter from poor reference clock, or ISI from long traces

Fix: Improve length matching, shorten trace length, add pre-emphasis if supported

Problem: Eye is too short (voltage closure)

Cause: Attenuation from long traces, impedance discontinuities, or excessive via count

Fix: Shorten traces, eliminate unnecessary vias, verify impedance through TDR simulation

Problem: Eye is distorted asymmetrically

Cause: Mode conversion from asymmetrical routing or reference plane discontinuities

Fix: Ensure both traces have identical routing environments, fix any split-plane crossings

Common Signal Integrity Problems and Solutions

Crosstalk

Crosstalk occurs when signals from adjacent traces couple into your differential pair. In high-density PCBs, this is the primary SI killer.

Mitigation:

Maintain minimum 3–5× trace width separation between pairs

Route high-speed pairs perpendicular to each other on adjacent layers

Use grounded guard traces for extremely sensitive signals

Reduce dielectric thickness to the reference layer (tighter coupling = less field spread)

Reflections

Reflections occur at any impedance discontinuity — connectors, vias, layer transitions, and impedance mismatches.

Mitigation:

Control impedance to ±5% along the entire trace length

Minimize vias and layer transitions

Use properly matched connectors

Avoid trace width changes (even pad entrances should be impedance-controlled)

Jitter

Jitter is the deviation of a signal edge from its ideal timing position. It comes in two flavors:

Random jitter (RJ): Caused by thermal noise, shot noise — unavoidable but should be minimized

Deterministic jitter (DJ): Caused by ISI, crosstalk, reflections, and power supply noise — design-dependent and fixable

Mitigation:

Reduce ISI through proper trace length and loss budgeting

Ensure clean power delivery to the transmitter and receiver

Minimize crosstalk through spacing and layer planning

Use spread-spectrum clocking if supported by the standard

Practical Design Checklist

Before sending your design to fabrication, verify:

Differential impedance simulated for your exact stackup (90Ω for USB 3.0, 100Ω for HDMI)

Both traces in each pair are length-matched within tolerance

Serpentine compensations placed near mismatch sources

No differential pair crosses a split in the reference plane

Via count is minimized and matched between traces in a pair

Ground stitching vias placed near all signal layer transitions

No 90° corners — use 45° or curved bends

AC coupling capacitors (USB 3.0 TX only) placed correctly

Pair-to-pair spacing meets minimum requirements

ESD protection components placed at connectors

Eye diagram simulation passed with margin

TDR simulation shows no impedance excursions beyond ±10%

Frequently Asked Questions

What is the difference between 90Ω and 100Ω differential impedance?

The difference is in the characteristic impedance of the differential pair, determined by trace geometry, spacing, and dielectric properties. USB 3.0 specifies 90Ω ±7% to optimize for its specific transmitter drive strength and receiver termination. HDMI specifies 100Ω ±10% based on TMDS signaling requirements. Using the wrong impedance causes reflections that degrade signal quality. You cannot use the same trace geometry for both — each requires its own stackup calculation and impedance simulation.

How do I measure intra-pair skew in my PCB design?

In your CAD tool, use the length matching analyzer to report the difference in routed length between D+ and D− traces. Convert length to time using the propagation velocity of your dielectric (approximately 6.7 ps/mm for FR-4, εr ≈ 4.3). For measurement verification, use a TDR (Time Domain Reflectometry) instrument or a high-bandwidth oscilloscope with differential probes to measure the actual time skew at the receiver end. The measured skew must be within the standard's specification (5 ps for USB 3.0, 10 ps for HDMI).

Can I route USB 3.0 and HDMI on the same PCB layer?

Yes, but maintain adequate spacing between them. The minimum recommended separation is 5× the trace width (or 3× the intra-pair gap, whichever is larger) between any USB 3.0 and HDMI differential pairs. If space is tight, consider routing them on different signal layers with a solid ground plane between them for isolation. Also be aware of the different impedance targets (90Ω vs 100Ω) — you'll need different trace geometries for each, even on the same layer.

Why does crossing a split plane destroy signal integrity?

High-speed return current follows the path of least impedance, which is directly beneath the trace in the reference plane (minimum loop area). When the reference plane has a split, the return current must find an alternate path — typically through parasitic capacitance or a long detour to a stitching capacitor. This creates a large current loop that acts as an antenna (increasing EMI), adds series inductance (causing reflections and impedance spikes), and converts differential energy to common-mode energy (degrading the eye). The impact can be 10–20 dB of additional EMI and significant eye closure.

What is the maximum trace length for USB 3.0 and HDMI differential pairs?

For USB 3.0 SuperSpeed, the maximum trace length on the PCB depends on your loss budget. The spec allows approximately 6 dB of channel insertion loss at 2.5 GHz (Nyquist frequency). With typical FR-4 loss of about 0.3–0.5 dB/inch at 2.5 GHz, this translates to roughly 12–20 inches (300–500 mm) maximum. However, if you have connectors, vias, and other discontinuities, the practical limit is shorter. For HDMI, the TMDS specification allows for cable lengths up to several meters, but PCB trace length should be minimized — typically under 6 inches (150 mm) on the source side and under 3 inches (75 mm) on the sink side, accounting for the total channel budget.

Do I need pre-emphasis or equalization for my differential pairs?

It depends on your trace length and data rate. For short traces (under 3 inches / 75 mm) at USB 3.0 speeds, the transmitter's default settings are usually sufficient. For longer traces, channel insertion loss causes ISI that closes the eye. Most modern USB 3.0 and HDMI PHYs support programmable pre-emphasis (boosting high-frequency components at the transmitter) and receiver equalization (compensating for channel loss at the receiver). Start with your PHY's recommended settings, then use IBIS-AMI simulations to optimize. If your eye diagram simulation shows insufficient margin with maximum pre-emphasis and equalization, you need to shorten the trace or use a lower-loss dielectric material.

External Resources

USB 3.0 Specification and Compliance — Official USB-IF documentation for SuperSpeed electrical requirements and compliance testing [4]

HDMI Specification — HDMI Forum's official specification covering TMDS electrical characteristics and compliance [5]

Texas Instruments: High-Speed Layout Guide — Practical PCB layout recommendations for differential pairs

Intel: USB 3.0 PCB Layout Guidelines — Intel's implementation guide for USB 3.0 routing

Sierra Circuits: Differential Pair Impedance Calculator — Online tool for calculating differential impedance based on your stackup

References

[1] Hall, S. H., & Hall, G. W. (2000). *High-Speed Digital System Design: A Handbook of Interconnect Theory and Design Practices*. Wiley.

[2] Bogatin, E. (2018). *Signal and Power Integrity Simplified* (3rd ed.). Prentice Hall.

[3] Thierauf, S. C. (2004). *High-Speed Circuit Board Signal Integrity*. Artech House.

[4] USB Implementers Forum. (2013). *Universal Serial Bus 3.0 Specification*. Revision 1.0.

[5] HDMI Forum. (2017). *HDMI Specification Version 2.1*.